3D Memory Data Line Structure With Metal Liner Capacitance Control
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Solution Overview
Problem
Current flash memory devices face challenges in reducing data line capacitance and maintaining resistance within desired specifications, which affects the performance and efficiency of memory operations in electronic devices.
Innovation Solution
The use of metal liner deposition in the fabrication of memory devices allows for controlled reduction of data line capacitance by selecting the thickness of dielectric layers and metal options such as ruthenium, tungsten, or titanium, avoiding pitch double and quad processes, and enabling well-controlled data line heights and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional flash memory fabrication processes are used, then manufacturing simplicity is maintained, but data line capacitance cannot be effectively reduced
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming dielectric layers with specific thicknesses, selective removal to create openings, deposition of metal liners in openings, and selective removal to form data lines. This segmentation allows precise control of data line capacitance through dielectric thickness selection while managing fabrication complexity through systematic process steps.
Solution Approach 2:
Different regions of the memory device are given different dielectric layer thicknesses: thicker dielectric in non-data line regions and thinner dielectric in data line regions. This local quality variation reduces data line capacitance where needed while maintaining structural integrity and electrical performance in other areas.
2Loss of energy
If data line capacitance is reduced by thinning dielectric layers, then capacitance decreases, but resistance control becomes difficult
Solution Approach 1:
The data line structure uses composite materials combining different dielectric layers with specific thicknesses and metal liner materials (such as ruthenium, tungsten, or titanium). This composite structure allows simultaneous optimization of capacitance (through dielectric thickness) and resistance (through metal selection and thickness), achieving both electrical performance targets.
Solution Approach 2:
The invention changes physical parameters of the data line structure: dielectric layer thickness, metal liner thickness, and metal material composition. By adjusting these parameters, the patent achieves the desired balance between capacitance reduction and resistance control, meeting both electrical specifications.
3Productivity
If pitch double and quad processes are used to reduce data line spacing, then density increases, but fabrication complexity and cost increase
Solution Approach 1:
Instead of reducing data line spacing in the planar dimension through complex pitch multiplication processes, the invention achieves density improvement by utilizing the vertical dimension through selective dielectric thickness control and metal liner deposition. This dimensional approach simplifies fabrication while maintaining high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces data line capacitance while maintaining resistance within specifications, enhancing the performance and efficiency of memory operations in electronic devices, including those used in IoT, automotive, and mobile applications.
Implementation Method 1
The use of metal liner deposition in the fabrication of memory devices allows for controlled reduction of data line capacitance by selecting the thickness of dielectric layers and metal options
Data Source
AI summary
A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.