3D Nonvolatile Memory Layout With Independent Decoder Placement
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Solution Overview
Problem
The reduction of size and manufacturing cost of vertical memory devices is limited due to the inclusion of peripheral circuits and wiring structures, which hinder high integration and electrical performance.
Innovation Solution
A nonvolatile memory device with a COP (Cell Over Periphery) or BVNAND structure where the peripheral circuit is formed below and the memory cell array is stacked on top, with pass transistors and drivers arranged independently, allowing for increased placement freedom and reduced circuit region and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral circuits and wiring structures are included in vertical memory devices, then the devices can function properly, but the device size increases and manufacturing cost increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked architecture where the memory cell array is positioned above the peripheral circuit in the vertical direction. This dimensional change allows both functional components to coexist without increasing the planar footprint, resolving the contradiction between functional performance and device size.
Solution Approach 2:
The memory device is segmented into distinct functional layers: a first semiconductor layer containing the memory cell array and a second semiconductor layer containing the peripheral circuit. This segmentation allows independent optimization of each layer and enables the peripheral circuit to be positioned beneath the memory cell array, reducing overall device size while maintaining functionality.
2Reliability
If peripheral circuits and wiring structures are included in vertical memory devices, then the devices can function properly, but manufacturing cost increases
Solution Approach 1:
The device is divided into separately manufacturable semiconductor layers that can be processed independently and then stacked. This segmentation enables modular manufacturing where each layer can be optimized for its specific function, reducing overall manufacturing complexity and cost while maintaining functional performance.
Solution Approach 2:
By moving the peripheral circuit to the vertical dimension beneath the memory cell array, the patent eliminates the need for extensive planar wiring structures, thereby reducing manufacturing complexity and cost associated with traditional lateral interconnections.
3Device complexity
If pass transistors and drivers are arranged in dependent patterns, then wiring is simplified, but placement freedom is reduced and circuit region increases
Solution Approach 1:
The address decoder is segmented into pass transistors in the first semiconductor layer and drivers in the second semiconductor layer. This spatial segmentation allows each component to be independently positioned and optimized without being constrained by dependent arrangement patterns, thereby increasing placement freedom while maintaining wiring simplicity through vertical integration.
Solution Approach 2:
By separating pass transistors and drivers into different vertical layers, the patent removes the constraint of planar arrangement patterns. This dimensional separation provides placement freedom for both components while maintaining electrical connectivity through vertical interconnections, resolving the contradiction between wiring simplicity and placement flexibility.
Data Source
AI summary
A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.