3D Non-Volatile Memory Interconnection Structure for Decoder Voltage Transfer

Solution Overview

Problem

Conventional 3D non-volatile memory devices with a PUC structure face increased operation time and chip size due to the high resistance of under-metal lines used for interconnections, which deteriorate chip performance.

Innovation Solution

The implementation of a non-volatile semiconductor memory device with a revised interconnection structure that includes a decoder below the cell region, featuring a first upper line above the cell region, a lower interconnection structure below, and vias to transfer word line voltage efficiently, utilizing conductive materials with lower resistance for upper metal lines and higher resistance materials only where necessary for under metal lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If under-metal lines are used for decoder interconnection in PUC structure, then decoder can be located below cell region, but signal transfer time increases due to higher resistance

Engineering Contradiction:

Improvedecoder layoutVSAvoidsignal transfer time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent changes the material parameter (resistance) of the metal lines by selectively forming first metal lines with lower resistance than second metal lines. This parameter change allows the decoder to be located below the cell region while compensating for the higher resistance of under-metal lines, thus reducing signal transfer time despite the PUC structure.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies different material qualities to different parts of the interconnection structure. First metal lines (upper metal lines) are formed with lower resistance material, while second metal lines (under metal lines) use conventional material. This local differentiation optimizes signal transfer for critical paths while maintaining the decoder below-cell-region placement.

Inventive Principle:

Principle #3Local quality

2Reliability

If under-metal lines are formed for decoder interconnection, then decoder connectivity is achieved, but chip size increases

Engineering Contradiction:

Improvedecoder connectivityVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent moves the decoder from a lateral arrangement to a vertical arrangement by placing it below the cell region. This dimensional change in the layout architecture allows decoder interconnection through the vertical stack (using under-metal and upper-metal lines) rather than requiring additional lateral space, thus achieving connectivity without increasing chip area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If conventional metal lines are used for both upper and under interconnections, then manufacturing is simplified, but operation characteristics deteriorate

Engineering Contradiction:

Improveinterconnection structure fabricationVSAvoidchip operation characteristics

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies different material qualities to different parts of the interconnection structure. First metal lines (upper metal lines) are formed with lower resistance material, while second metal lines (under metal lines) use conventional material. This local differentiation optimizes signal transfer for critical paths while maintaining the decoder below-cell-region placement.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the material parameter (resistance) of the metal lines by selectively forming first metal lines with lower resistance than second metal lines. This parameter change allows the decoder to be located below the cell region while compensating for the higher resistance of under-metal lines, thus reducing signal transfer time despite the PUC structure.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces signal transfer time and prevents chip size increase by optimizing the interconnection structure, enhancing chip operation characteristics.

Implementation Method 1

a lower interconnection structure formed below the cell region... a word line voltage is transferred from the first upper line through the first via, the lower interconnection structure, and the decoder to the cell region

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9805768B2Three-dimensional (3D) non-volatile semiconductor memory device for loading improvement

Publication Date: 2017.10.31 SK HYNIX INC

AI summary

A three-dimensional (3D) non-volatile semiconductor memory device is disclosed. The three-dimensional (3D) non-volatile semiconductor memory device includes: a cell region having a plurality of memory cells; a page buffer formed to store data of the cell region in units of a page; a decoder formed below the cell region, configured to provide a word line voltage to word lines of the cell region; a first upper line formed above the cell region, configured to transfer the word line voltage; a lower interconnection structure formed below the cell region, configured to transfer the word line voltage to the decoder; and a first via disposed between the cell region and the page buffer, configured to couple the first upper line to the lower interconnection structure.