3D Memory Above-Substrate Decoding Stage
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Solution Overview
Problem
The manufacturing cost of three-dimensional memory (3D-M) is high due to dense contact vias, which limit design flexibility and reduce memory density, making it challenging to integrate with substrate circuits and realize three-dimensional integrated circuits (3D-IC) and system-on-a-chip (SoC) designs.
Innovation Solution
Incorporating above-substrate decoding stages with transistors that allow sharing of contact vias among memory levels, reducing the number of contact-via sets and enabling interconnects to pass through, thus facilitating shorter peripheral lengths and higher array efficiency, and increasing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dense contact vias are used to couple memory levels to substrate circuits, then reliability of signal transmission is improved, but manufacturing cost increases and design flexibility is reduced
Solution Approach 1:
The patent divides the decoding function into two parts: substrate decoders remain on the substrate, while additional decoding stages are placed above the substrate in the memory levels. This segmentation allows contact vias to be shared among multiple memory levels, reducing their density requirements while maintaining signal transmission reliability.
Solution Approach 2:
The patent moves part of the decoding functionality from the substrate plane to the vertical dimension by placing decoding stages above the substrate. This dimensional transition enables shared contact via structures that serve multiple memory levels, reducing the horizontal density of contact vias and lowering manufacturing costs.
2Reliability
If dense contact vias are used to couple memory levels to substrate circuits, then signal transmission reliability is improved, but memory density is reduced
Solution Approach 1:
By segmenting the decoding function across substrate and above-substrate stages, the patent enables shared contact via structures. This reduces the number of dedicated contact vias per memory level, increasing the proportion of array area available for storage and thereby improving memory density.
Solution Approach 2:
The above-substrate decoding stages serve multiple memory levels simultaneously, making the contact vias that connect to these stages universal resources. This multi-functionality reduces the total number of contact vias needed, freeing up space for additional memory cells and improving overall memory density.
3Reliability
If dense contact vias are used to couple memory levels to substrate circuits, then signal transmission reliability is improved, but array efficiency is reduced
Solution Approach 1:
The patent segments the decoding architecture into substrate-level and above-substrate components. This segmentation allows contact vias to serve multiple memory levels through shared above-substrate decoding stages, reducing peripheral overhead and improving the ratio of useful array area to total area, thereby enhancing array efficiency.
Solution Approach 2:
By placing decoding stages above the substrate, the patent creates a three-dimensional decoding architecture. This dimensional change enables shared contact via structures that reduce peripheral lengths and improve array efficiency, while maintaining signal transmission reliability through the robust substrate decoder foundation.
4Reliability
If dense contact vias are used to couple memory levels to substrate circuits, then signal transmission reliability is improved, but design flexibility is reduced
Solution Approach 1:
The patent segments the decoding architecture into flexible above-substrate stages and stable substrate decoders. This segmentation provides design flexibility by allowing different configurations of above-substrate decoding stages for different memory levels, while maintaining reliable signal transmission through the fixed substrate decoder infrastructure.
Solution Approach 2:
The above-substrate decoding stages provide design flexibility by enabling various interconnection schemes and decoder configurations in the vertical dimension. This dimensional freedom allows designers to optimize for different applications while maintaining reliable signal transmission through the substrate connection, thereby improving adaptability without sacrificing reliability.
Data Source
AI summary
The above-substrate decoding stage of a compact three-dimensional memory (3D-Mc) could be an intra-level decoding stage, an inter-level decoding stage, or a combination thereof. For the intra-level decoding stage, contact vias can be shared by address-lines in the same memory level; for the inter-level decoding stage, contact vias can be shared by address-lines from different memory levels.