3D Memory Devices With Deep Isolation Structures
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, necessitating a transition to three-dimensional (3D) memory architectures to enhance memory density.
Innovation Solution
A three-dimensional capacitor structure for memory devices is developed, involving the formation of peripheral circuitry and memory arrays on separate substrates, with through-silicon isolation structures to prevent crosstalk and improve isolation between adjacent devices, allowing for increased memory density and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication processes, then memory density is improved, but feature sizes approach a lower limit making planar processes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The 3D memory array is formed on a separate substrate and then bonded to the peripheral circuitry substrate, enabling vertical stacking and significantly increasing memory density without further reducing lateral feature sizes. This dimensional change resolves the contradiction by providing a new scaling pathway that avoids the limitations of continued planar scaling.
Solution Approach 2:
The memory device is divided into two separate substrates: one for peripheral circuitry and another for the memory array. This segmentation allows each substrate to be optimized independently for its specific function, with the memory array substrate可以采用不同的工艺优化存储单元，而外围电路基板可以优化读写控制电路，从而降低整体制造难度和成本。
2Quantity of substance
If three-dimensional memory architecture is implemented to address density limitation, then memory density is improved, but isolation structures are needed to prevent crosstalk between adjacent devices
Solution Approach 1:
The isolation system is segmented into multiple levels: shallow trench isolation (STI) structures at the device level and deep isolation trenches at the substrate level. This multi-level segmentation provides comprehensive crosstalk prevention while allowing each isolation layer to be optimized for its specific function, balancing effectiveness with manufacturing complexity.
Solution Approach 2:
Isolation structures extend into the vertical dimension with deep isolation trenches penetrating through the substrate thickness. This vertical isolation approach complements lateral STI structures, providing three-dimensional isolation that effectively prevents crosstalk while maintaining a compact footprint for high-density memory arrays.
3Speed
If peripheral circuitry and memory array are formed on separate substrates and bonded together, then interconnect lengths are reduced improving performance, but substrate bonding processes add manufacturing complexity
Solution Approach 1:
The device is segmented into separately fabricated substrates that are subsequently bonded together. This allows each substrate to be manufactured using optimized processes for its specific function, with bonding serving as a final assembly step that enables performance benefits while managing manufacturing complexity through process separation.
Solution Approach 2:
Both substrates are prepared in advance with all necessary circuitry, interconnect structures, and isolation features before bonding. This preliminary fabrication and preparation of each substrate independently simplifies the overall manufacturing process by dividing complex tasks into manageable stages, reducing the complexity of the bonding operation itself.
Data Source
AI summary
A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.