3D Memory Routing Structure for CMOS Deep-Via Integration
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Solution Overview
Problem
The integration of a 3D memory structure with a CMOS device is challenging due to complex circuit connections, making it difficult to achieve high-density memory stacking and efficient routing of source and bit lines.
Innovation Solution
A novel 3D semiconductor memory structure with a monolithic CMOS process is developed, featuring a 3D memory structure with TFTs arranged in three directions, utilizing conductive pillars as deep vias for connecting global source and bit lines to active structures through a multi-layer dielectric stack, enabling efficient routing and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D memory structure is integrated with a CMOS device, then memory capacity is increased, but circuit connection complexity increases
Solution Approach 1:
The patent transitions from traditional 2D memory architecture to a 3D stacked architecture where memory cells are arranged vertically across multiple layers. This dimensional change increases memory capacity within the same footprint while requiring novel interconnect structures (through-silicon vias, stacked contacts) to manage the increased connection complexity in three-dimensional space.
Solution Approach 2:
The patent implements nested interconnect structures where multiple conductive layers and via structures are stacked vertically to connect different memory layers to CMOS circuitry. The through-silicon vias and stacked contacts create nested pathways that route signals through multiple levels, effectively nesting connection paths to manage complexity.
2Area of stationary object
If memory cells are scaled down to increase capacity, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Instead of continuing to scale memory cells horizontally in 2D, the patent stacks memory cells vertically in the third dimension. This approach increases capacity by utilizing vertical space rather than reducing individual cell area, thereby avoiding the escalating manufacturing precision requirements that would result from further horizontal scaling.
3Ease of manufacture
If a novel SL/BL routing is implemented, then integration ease is improved, but device complexity increases
Solution Approach 1:
The patent segments the source line and bit line routing into separate conductive layers within the interconnect structure. By dividing the routing functions across multiple dedicated layers and using through-silicon vias for vertical connections, the patent simplifies the manufacturing process while managing the inherent complexity of 3D routing through systematic segmentation of signal paths.
Data Source
AI summary
A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.