3D Memory Routing Through Deep Vias for CMOS Integration
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Solution Overview
Problem
The integration of a 3D memory structure with a CMOS device is complicated due to the difficulty in connecting the circuitry, necessitating a novel source line/bit line routing to facilitate monolithic integration.
Innovation Solution
A semiconductor device with a 3D memory structure featuring a novel circuit routing that includes a plurality of conductive pillars and interconnect layers, allowing for efficient electrical connections between the 3D memory and CMOS device through global source and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D memory structure is integrated with a CMOS device, then memory capacity is increased, but circuit connection complexity increases
Solution Approach 1:
The patent transitions from traditional 2D planar interconnect routing to 3D vertical routing through conductive pillars that extend through the memory structure. This dimensional change allows source and bit lines to connect to memory cells in multiple layers simultaneously, increasing memory capacity while managing connection complexity through vertical stacking rather than lateral expansion.
Solution Approach 2:
The patent segments the interconnect structure into distinct conductive pillars that serve as vertical interconnect elements, separating the routing function into modular components. Each conductive pillar independently connects specific source and bit lines to corresponding memory cells, simplifying the overall connection architecture by breaking down the complex routing problem into manageable discrete elements.
2Ease of manufacture
If conventional routing is used in 3D memory structure, then manufacturing process is simpler, but integration efficiency decreases
Solution Approach 1:
The conductive pillars are formed as part of the memory structure fabrication process itself, rather than as separate post-processing interconnect elements. The pillars are created during the standard BEOL (back-end-of-line) CMOS manufacturing sequence, performing the routing function in advance as the memory structure is being built, thereby eliminating additional manufacturing steps while enabling efficient 3D integration.
3Area of stationary object
If 3D memory architecture is implemented, then area utilization is improved, but circuit routing difficulty increases
Solution Approach 1:
The patent resolves routing difficulties by moving from 2D lateral routing to 3D vertical routing through conductive pillars. This allows multiple source and bit lines to be stacked vertically and connected to corresponding memory cells through the depth of the structure, achieving high area utilization while simplifying routing through the vertical dimension rather than requiring complex lateral wire crossings and vias.
Data Source
AI summary
A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.