3D Memory Interconnect Layout With Dendritic Low-Resistance Paths
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Solution Overview
Problem
Three-dimensional memory devices with low-resistance semiconductor interconnection lines face high series resistance issues due to long horizontal wire lengths, affecting reading and writing performance, and applying metal silicide layers leads to redundant connections that short-circuit storage media, causing functional failures.
Innovation Solution
A high-density three-dimensional memory structure with a dendritic interdigitated base structure, featuring alternating conductive and insulating layers, curved division trenches, and memory holes with vertical electrodes, reducing series resistance by using wider trunk structures with lower resistance compared to slender branches, and maintaining low manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If low-resistance semiconductor materials (e.g., highly doped polycrystalline silicon) are used as horizontal interconnection lines, then the manufacturing process is simple and cost is low, but the resistivity of the interconnection lines is relatively high due to long wire lengths (hundreds to thousands of microns)
Solution Approach 1:
The patent divides the base structure into multiple stacking layers with alternating conductive and insulating medium layers. This segmentation creates multiple shorter vertical pathways for current flow, effectively reducing the equivalent horizontal wire length and series resistance while maintaining the simple semiconductor material process
Solution Approach 2:
The patent transitions from traditional planar horizontal interconnection to a three-dimensional vertical stacking architecture. By moving interconnection pathways to the vertical dimension through alternating conductive and insulating layers, the effective path length is reduced despite long horizontal distances, solving the high resistance problem while keeping manufacturing simple
2Quantity of substance
If the length of horizontal wires is increased to achieve high-density storage, then storage capacity increases, but series resistance of horizontal conductors increases significantly
Solution Approach 1:
The patent solves the series resistance problem by transitioning from horizontal to vertical current pathways through the alternating conductive and insulating medium layers stacking structure. This dimensional change allows high storage density with long horizontal wire lengths while maintaining low series resistance through the vertical stacking architecture
Data Source
AI summary
A high-density three-dimensional memory device with interconnection of low resistance and a manufacturing method thereof are provided. The device includes an underlying circuit part, and a base structure disposed on the underlying circuit part. The base structure includes first conductive medium layers and insulating medium layers which are alternately stacked on each other from bottom to top. The base structure has dendritic interdigitated structure, the dendritic interdigitated structure is composed of two dendritic structures. The dendritic structure includes a trunk and branches connected to and perpendicular to the trunk. A preset number of memory holes are formed in a curved division trench between the branches and an external structure. A vertical electrode perpendicular to the bottom surface of the base structure is disposed in the memory hole, a storage medium required for a preset memory type is disposed between the vertical electrode and an inner wall of the memory hole.