3D Memory Semiconductor Structure with Dense Vertical Interconnects
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through-Silicon Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) to construct configurable logic, allowing for the creation of multiple connections less than one micron in size, enabling the use of 3D IC technology for various device applications, and incorporating modular approaches with Through-Silicon-Via (TSV) for constructing configurable systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent implements re-programmable antifuse technology that allows the semiconductor device to be dynamically reconfigured after fabrication. This enables the same physical device to adapt to different logic family requirements through electrical programming rather than requiring separate mask sets for each product variant, thereby improving flexibility while maintaining manufacturing efficiency
Solution Approach 2:
The invention creates a universal fabrication platform using re-programmable antifuse devices that can serve multiple product configurations. A single manufactured device can be programmed to implement different logic functions, making the fabrication process universally applicable to various commercial products without requiring dedicated mask sets for each application
2Productivity
If existing 3D IC technologies are used, then connections between levels are established, but large Through-Silicon Vias restrict the number of connections
Solution Approach 1:
The patent segments the connection structure by replacing large Through-Silicon Vias with multiple smaller interconnect structures at different metal layers. Instead of relying on a single large via per connection point, the invention distributes connections across multiple smaller vias and metal traces, increasing the total number of connections that can be made without requiring proportionally larger TSVs
Solution Approach 2:
The invention transitions from a vertical connection paradigm (large TSVs going straight through the silicon) to a multi-dimensional interconnect architecture using multiple metal layers. Connections are established not only vertically through TSVs but also horizontally and diagonally across multiple metal planes, effectively adding dimensional complexity to increase connection density without increasing TSV size
Data Source
AI summary
A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.