3D Variable Resistance Memory Layout for Higher Cell Density
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Solution Overview
Problem
The density of two-dimensional variable resistance memory devices is limited by the area occupied by unit memory cells, hindering further integration improvements.
Innovation Solution
A three-dimensional memory device architecture is developed, featuring vertically arranged word lines and bit lines with shared global bit lines and a staircase-shaped pad structure, reducing the area required for electrical connections and increasing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional variable resistance memory device with cross point arrangement is used, then the structure is simple and easy to manufacture, but the memory density is limited due to the area occupied by unit memory cells
Solution Approach 1:
The patent transitions from a two-dimensional memory cell arrangement to a three-dimensional structure by introducing vertical stacking of word lines and bit lines. Multiple word line groups are arranged at different vertical levels, with bit lines extending vertically to intersect with word lines from different levels, creating a 3D cross-point architecture that increases storage capacity per unit area
2Quantity of substance
If more memory cells are arranged in a given area to increase density, then the memory density improves, but the area occupied by electrical connection structures increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange multiple word line groups at different height levels. Bit lines extend vertically to connect with word lines from multiple levels, enabling electrical connections in the vertical dimension rather than only in the horizontal plane, thereby reducing the footprint area required for connections
Solution Approach 2:
The patent implements a hierarchical connection structure where bit lines at different vertical levels are nested within the same horizontal footprint area. Multiple word line groups are stacked vertically, with each group containing multiple word lines, creating a nested arrangement that maximizes space utilization
Data Source
AI summary
A three-dimensional memory device includes: a plurality of word line groups including a plurality of word lines; a plurality of bit line groups extending in a vertical direction and including a plurality of bit lines spaced apart from the plurality of word lines; a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines and including a switching component and a variable resistance memory component; a plurality of global bit line groups connected to the plurality of bit line groups, wherein each of the plurality of global bit line groups includes a plurality of global bit lines electrically connected to a plurality of bit lines included in one bit line group, respectively; and a pad structure including a plurality of connection units and a plurality of pad layers, wherein the plurality of connection units are connected to the plurality of word line groups.