3D Semiconductor Memory Structure for Higher Storage Density
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Solution Overview
Problem
Conventional semiconductor structures, such as DRAM, are two-dimensional, leading to low storage density and integration challenges that hinder meeting memory capacity requirements.
Innovation Solution
A method is developed to form a three-dimensional semiconductor structure by creating a stacked layer of semiconductor pillars on a substrate, with a horizontal capacitor, vertical word line, and horizontal bit line, transforming the conventional two-dimensional structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a two-dimensional semiconductor structure is used, then the device complexity is low and manufacturing is easier, but the storage density and integration are low
Solution Approach 1:
The patent transforms the conventional two-dimensional semiconductor structure into a three-dimensional structure by stacking multiple semiconductor layers vertically. Each layer contains semiconductor pillars arranged in a grid pattern, with capacitors formed between adjacent layers. This vertical stacking approach increases storage density by utilizing the third dimension (height) rather than only expanding in the planar direction, thereby resolving the contradiction between storage density and structural complexity.
2Quantity of substance
If semiconductor layers are stacked vertically to increase integration, then storage density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the semiconductor structure into multiple discrete layers, each containing semiconductor pillars, capacitors, and interconnect structures. By segmenting the device into modular layers that can be independently formed and then stacked, the manufacturing process can focus on achieving precision within each layer rather than requiring perfect precision across the entire three-dimensional structure. This segmentation approach maintains high integration while managing manufacturing precision requirements.
3Reliability
If bit lines are extended to cover semiconductor pillars, then electrical performance improves, but resistance increases
Solution Approach 1:
The patent implements different interconnect structures at different locations within the semiconductor device. Bit lines are configured to extend over semiconductor pillars in regions where electrical connection is critical, while other regions may use different interconnect approaches. This localized optimization allows the bit lines to provide necessary electrical performance where needed without unnecessarily increasing overall resistance, thereby resolving the contradiction between electrical performance and resistance.
Data Source
AI summary
Embodiments relates to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a stacked layer on a top surface of a substrate, where the stacked layer includes a plurality of semiconductor layers spaced along a first direction, the stacked layer includes a transistor region, and a capacitor region and a bit line region; forming a capacitor extending along the second direction in the capacitor region; forming a word line in the transistor region, the word line extending along the first direction; and forming a bit line in the bit line region, the bit line extending along the third direction.