3D Semiconductor Memory De-skewing Interlayer Timing Delay
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Solution Overview
Problem
Semiconductor memory devices with a 2D structure have reached integration limits, necessitating a 3D stacked structure to overcome these limitations, while also requiring methods to minimize data skew and reduce data input/output time differences between layers due to their physical structure.
Innovation Solution
A semiconductor device with a 3D stacked structure, including a first and second semiconductor area with controlled access timings to ensure identical time delays for data output from each layer, using a method that adjusts physical distances of access signals and data paths to compensate for skew without adding switching or delay devices, and employing a common wordline and bitline configuration for synchronized data delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D stacked structure is implemented to overcome 2D integration limits, then integration density is improved, but data skew and input/output time differences between layers increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-configuring compensating delay values for each layer based on their physical distances from the I/O interface. The system determines the optimal delay compensation for each layer in advance during device fabrication or initialization, so that when data is transferred, the skew is already compensated without requiring real-time adjustment mechanisms.
Solution Approach 2:
The patent changes the timing parameter of data access for each layer by introducing variable delay compensation values. By adjusting the access timing parameters differently for each layer based on their physical position, the system compensates for the propagation time differences caused by the 3D stacked structure, thereby eliminating data skew while maintaining high integration density.
2Manufacturing precision
If access timings are controlled to compensate for interlayer delay, then data skew is reduced, but access complexity increases
Solution Approach 1:
The patent merges the delay compensation function with the existing wordline control mechanism. Instead of adding separate delay circuits for each layer, the system combines the timing control functionality into the wordline generation logic, using the same control infrastructure to achieve both layer selection and skew compensation, thereby reducing overall system complexity.
Solution Approach 2:
The system implements self-service by automatically determining and applying the appropriate delay compensation for each layer based on pre-stored timing information. The control logic autonomously adjusts access timings without requiring external intervention or complex real-time calculations, simplifying the control mechanism while achieving precise skew compensation.
3Loss of time
If physical distances of access signals are adjusted to compensate for skew, then data timing synchronization is improved, but device structure complexity increases
Solution Approach 1:
The patent addresses the timing synchronization problem by introducing a temporal dimension to the control mechanism rather than modifying the physical signal paths. Instead of equalizing physical distances, the system uses differential timing control in the time domain, applying variable delay compensation to each layer's access signals, which achieves synchronization without altering the 3D physical structure.
Data Source
AI summary
A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.