3D Memory Device Using Transition Metal Dichalcogenide Channel
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Solution Overview
Problem
Conventional three-dimensional NAND memory devices with polysilicon channels suffer from defective interfaces and plasma damage, leading to degraded charge carrier mobility, cell current, and reliability issues due to the use of amorphous silicon layers.
Innovation Solution
A monolithic three-dimensional memory device employing a metal dichalcogenide channel, such as MoS2, with a thickness of up to eight atomic layers, and an interfacial high-k dielectric layer to improve interface quality and reduce operational voltages, thereby enhancing charge carrier mobility and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If two layers of amorphous silicon are used to form the semiconductor channel, then the channel thickness can be controlled in the range of 15 nm to 20 nm, but a defective interface is formed between the two polysilicon layers leading to degradation of charge carrier mobility and cell current
Solution Approach 1:
The patent changes the material parameter from amorphous silicon to crystalline semiconductor material, which eliminates the interface defects between layers while maintaining the desired channel thickness of 15-20 nm, thereby improving charge carrier mobility
Solution Approach 2:
The patent uses a composite structure combining crystalline semiconductor material with high-k dielectric materials (such as hafnium oxide, aluminum oxide, or silicon oxide) to create a channel that avoids the defects of pure amorphous silicon while maintaining electrical performance
2Ease of manufacture
If anisotropic etch is used to form the memory opening, then the underlying semiconductor material can be physically exposed, but re-sputtered etch ions damage the cover amorphous silicon layer leading to plasma damage within the semiconductor channel
Solution Approach 1:
The patent introduces a sacrificial cover layer that is intentionally designed to be removed during the anisotropic etch process, protecting the underlying channel material from plasma damage while enabling efficient memory opening formation
Solution Approach 2:
The sacrificial cover layer acts as an intermediary protective element during the etching process, absorbing the harmful plasma effects and being subsequently removed, thereby preventing damage to the final semiconductor channel
3Device complexity
If conventional polysilicon channel is used, then the device structure is simpler, but the device power consumption is higher and boosting potential is limited
Solution Approach 1:
The patent changes the electrical parameters of the channel material by using crystalline semiconductor with high-k dielectric interfaces, which reduces power consumption and enhances boosting potential while maintaining structural simplicity
Data Source
AI summary
A monolithic three-dimensional memory device contains a high mobility metal dichalcogenide channel. A stack of alternating layers comprising first material layers and second material layers is formed over a substrate. A memory opening is formed through the stack of alternating layers. A memory film is formed in the memory opening. A metal dichalcogenide channel is formed on an inner sidewall of the memory film. A dielectric core is formed within the metal dichalcogenide channel. A stack of titanium and gold may be employed to form a drain region to enhance contact. A hafnium oxide, aluminum oxide or hafnium aluminum oxide hafnium aluminum oxide layer may be employed on either side, or on both sides, of the metal dichalcogenide channel to enhance the mobility of electrons in the metal dichalcogenide channel.