3D Memory Capacitor Layout Beyond DRAM Dielectric Scaling Limits
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Solution Overview
Problem
The miniaturization of dynamic random access memory (DRAM) is limited by the size of cylindrical capacitors, which restricts further reduction in size and increases in storage capacity due to physical limitations of the intermediate dielectric layer, making it difficult to achieve both small size and large storage capacity in limited layout space.
Innovation Solution
A three-dimensional memory structure with capacitors having a thin-film layer structure, where the first and second electrodes and dielectric layers are stacked perpendicular to the substrate, allowing multiple storage array layers to be superimposed, increasing storage capacity while simplifying the manufacturing process and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If cylindrical capacitors are used in DRAM, then the structure is simple to manufacture, but the size cannot be further reduced due to physical limits of the intermediate dielectric layer
Solution Approach 1:
The patent transitions from a planar cylindrical capacitor structure to a three-dimensional stacked capacitor structure with multiple electrodes and dielectric layers arranged vertically. This dimensional change allows storage capacity to increase in the vertical direction rather than being constrained by lateral expansion, thereby reducing the overall footprint while maintaining manufacturing feasibility through standard thin-film deposition processes.
Solution Approach 2:
The patent implements a nested structure where multiple capacitor elements are stacked vertically with each capacitor consisting of nested electrodes and dielectric layers. The first electrode, first dielectric layer, and second electrode are stacked sequentially, creating a compact nested arrangement that maximizes storage density within the vertical space while avoiding the physical limitations of lateral scaling.
2Area of stationary object
If the diameter of cylindrical capacitor is reduced to 2×nm process level, then layout space is reduced, but the thickness of intermediate dielectric layer reaches quantum tunneling physical limit
Solution Approach 1:
Instead of continuing to reduce the lateral dimensions of cylindrical capacitors to the point where dielectric thickness reaches quantum tunneling limits, the patent redistributes storage capacity into the vertical dimension through stacked capacitor structures. This allows the dielectric layers to maintain sufficient thickness for reliability while achieving higher density through multi-layer stacking rather than lateral compression.
3Quantity of substance
If thin-film layer structure capacitors are used, then storage capacity increases in limited layout space, but manufacturing process becomes more complex
Solution Approach 1:
The patent segments the storage function into multiple discrete capacitor units stacked vertically, with each unit comprising separated electrodes and dielectric layers. This segmentation allows independent optimization of each layer's thickness and material properties, enabling high storage capacity while maintaining manufacturing control through standardized thin-film deposition processes for each segment.
Solution Approach 2:
The stacked capacitor structure serves multiple functions simultaneously: the vertical stacking provides both increased storage capacity and reduced footprint, while the modular electrode-dielectric-electrode units can be manufactured using standard semiconductor thin-film processes. This multi-functionality resolves the apparent complexity by demonstrating that the structure achieves multiple goals through a unified manufacturing approach.
4Quantity of substance
If multiple storage array layers are superimposed, then storage capacity increases, but manufacturing difficulty and defect states increase
Solution Approach 1:
The patent divides the multi-layer storage structure into repetitive modular units, each consisting of electrode-dielectric-electrode sequences. This segmentation enables the use of identical thin-film deposition and patterning processes for each layer, ensuring consistent manufacturing precision across multiple storage array layers while achieving high storage capacity through vertical stacking.
Data Source
AI summary
A three-dimensional memory includes a substrate and a storage array layer. The substrate is on a plane that extends in a first direction and a second direction. The storage array layer includes at least one storage structure, and the storage structure includes N capacitors disposed side by side on the substrate. Each of the N capacitors includes a first electrode, a first dielectric layer, and a second electrode that are sequentially stacked on the substrate in a third direction away from the substrate, N≥2, and N is an integer. The three-dimensional memory is configured to store data.