3D Memory Dielectric Layer Planarization for Staircase Step Height
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The thinning and planarization of dielectric material layers in 3D NAND memory devices are challenging due to excessive thickness and time-consuming processes, leading to cost issues and potential defects in surface evenness, especially as the number of levels increases.
Innovation Solution
Polishing the photoresist layer instead of etching it, allowing the remaining photoresist portion to provide protection during dielectric material etching, which reduces the step height and facilitates more controlled and efficient polishing, resulting in improved surface evenness and reduced fabrication time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching and polishing processes are used to reduce dielectric material layer thickness, then the desired thickness is achieved, but the process becomes time-consuming and increases fabrication cost
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial dielectric material layer before the main dielectric material layer. This sacrificial layer is etched away first, creating recesses that allow the subsequent main dielectric layer to be deposited at a reduced thickness, eliminating the need for extensive post-deposition polishing and reducing overall fabrication time.
Solution Approach 2:
The patent segments the dielectric material formation into two distinct parts: a sacrificial dielectric material layer and a main dielectric material layer. The sacrificial layer serves as a temporary structure that facilitates controlled thickness reduction through selective etching, while the main layer provides the final functional dielectric structure, thereby optimizing the overall thickness control process.
2Manufacturing precision
If extensive polishing is performed to planarize the dielectric material layer, then surface evenness is improved, but fabrication cost increases and defects may be introduced
Solution Approach 1:
The patent performs preliminary action by creating recesses in the sacrificial dielectric material layer through selective etching before depositing the main dielectric layer. This pre-formation of depth variations eliminates the need for extensive subsequent polishing to achieve planarity, as the main dielectric layer naturally conforms to the underlying topography, reducing fabrication cost and minimizing defect introduction.
3Reliability
If the dielectric material layer is made thicker to ensure adequate insulation, then insulation performance is improved, but the polishing process becomes more difficult and time-consuming
Solution Approach 1:
The patent segments the dielectric function into two layers: a sacrificial dielectric material layer that provides the necessary thickness for insulation during fabrication, and a main dielectric material layer that can be thinner since it doesn't need to provide the primary insulation function. This segmentation allows the overall structure to maintain adequate insulation while enabling more efficient polishing processes.
Solution Approach 2:
The patent employs a disposable sacrificial dielectric material layer that is intentionally made thick to ensure adequate insulation during fabrication. This sacrificial layer is subsequently etched away and discarded, having served its purpose of enabling controlled thickness reduction and planarity improvement without requiring the final dielectric structure to be excessively thick.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the step height between array and staircase regions, enhancing surface evenness and reducing the time and cost of the polishing process, providing a stable base for subsequent fabrication steps.
Implementation Method 1
Chemical mechanical polishing (CMP, a.k.a. chemical mechanical planarization) is a process of smoothing wafer surface with the combination of chemical etching and free abrasive mechanical polishing.
Implementation Method 2
Etching refers to any process that can remove material from a wafer. Chemical mechanical polishing (CMP, a.k.a. chemical mechanical planarization) is a process of smoothing wafer surface with the combination of chemical etching and free abrasive mechanical polishing.
Data Source
AI summary
Methods for forming a 3D memory device are provided. A method includes the following operations. A stack structure is formed in a staircase region and an array region. A dielectric material layer is formed over the array region and the staircase region. An etch mask layer is coated over the dielectric material layer. The etch mask layer, on a first surface away from the dielectric material layer, is planarized. The dielectric material layer and a remaining portion of the etch mask layer are etched to form a dielectric layer over the staircase region and the array region.