3D Memory Array Architecture for Dense Cells With Dielectric Reliability
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Solution Overview
Problem
Existing memory devices face challenges in increasing memory cell density, reducing power consumption, and decreasing manufacturing costs while maintaining data retention and reliability.
Innovation Solution
The development of a three-dimensional (3D) vertical self-selecting memory array with increased density of memory cells, achieved through an arrangement of conductive contacts and layers of conductive and insulative materials, which reduces spacing between memory cells while maintaining dielectric thickness for voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional vertical architecture is implemented, then memory cell density is increased, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory architecture to three-dimensional vertical architecture by stacking multiple decks of memory cells vertically. Each deck contains multiple layers of word lines and bit lines arranged in alternating patterns, with memory cells formed at the intersections. This vertical stacking enables significantly higher memory cell density within the same footprint area while maintaining manufacturability through systematic layer-by-layer fabrication processes.
2Quantity of substance
If spacing between memory cells is reduced, then memory cell density increases, but control of cell thickness and dimension becomes more difficult
Solution Approach 1:
The memory array is divided into multiple discrete decks, with each deck containing a specific number of memory cell layers (e.g., 16 layers per deck). Each deck is further segmented into alternating layers of first and second conductive materials, forming distinct word line and bit line planes. This segmentation allows for precise control of individual layer thicknesses and dimensions while enabling reduced spacing between cells through standardized repetitive fabrication steps for each layer.
3Reliability
If dielectric thickness is maintained for voltage application, then reliability is improved, but memory cell density decreases
Solution Approach 1:
Different dielectric materials are used in different locations within the memory structure to optimize both reliability and density. First dielectric material is employed in regions requiring high voltage breakdown strength (such as between alternating conductive layers), while second dielectric material with different properties is used in other regions. This local differentiation allows maintenance of adequate dielectric thickness for reliable voltage application in critical areas while reducing dielectric thickness in non-critical areas to increase overall memory cell density.
Data Source
AI summary
Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.