3D Memory Dielectric Thickness Tuning for Channel Width Variation
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Solution Overview
Problem
In 3D memory devices, the variation in channel hole widths and dielectric layer thicknesses leads to undesirable topography, affecting programming/erase speed and memory cell performance, resulting in non-uniform threshold voltages and increased susceptibility to read operations and erase state coupling effects.
Innovation Solution
The thickness of dielectric layers in 3D memory devices is made inversely proportional to the width of the channel structure along the vertical direction, compensating for the impact of channel width variations and improving the uniformity and stability of memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel hole width is reduced to increase memory density, then the memory density is improved, but the etching process becomes more restrictive and manufacturing precision deteriorates
Solution Approach 1:
The patent applies local quality by making the dielectric layer thickness non-uniform, specifically thicker at the bottom of the channel hole and thinner at the top. This localized variation in dielectric thickness compensates for the narrow channel width effects, improving etching uniformity and manufacturing precision while maintaining high memory density
Solution Approach 2:
The patent changes the thickness parameter of the dielectric layer from uniform to non-uniform distribution. By adjusting the dielectric layer thickness to be inversely proportional to the channel width, the patent optimizes the etching process and improves manufacturing precision without sacrificing memory density
2Ease of manufacture
If uniform dielectric layer thickness is used, then the fabrication process is simplified, but the memory cell performance uniformity deteriorates due to channel width variations
Solution Approach 1:
The patent implements local quality by varying the dielectric layer thickness according to the channel width at different depths. This localized adjustment ensures that memory cells experience more uniform electric fields, improving performance uniformity and reliability while maintaining reasonable fabrication complexity
3Adaptability or versatility
If the channel structure width varies to accommodate different memory cell requirements, then the adaptability is improved, but the threshold voltage distribution uniformity deteriorates
Solution Approach 1:
The patent changes the dielectric layer thickness parameter to be inversely proportional to the channel width. This parameter adjustment compensates for width variations, ensuring uniform threshold voltage distribution across different memory cell configurations while maintaining the adaptability of the 3D memory architecture
Data Source
AI summary
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.