3D Memory Array Digit Line Layout for Faster, Denser Reads
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Solution Overview
Problem
Conventional vertical memory array architectures in microelectronic devices, such as 3D NAND Flash memory devices, face challenges in improving performance and reducing feature sizes while maintaining high integration density, as they can hinder data transfer rates and increase power consumption.
Innovation Solution
The introduction of local and global digit line structures within a microelectronic device design, including a stack structure with alternating conductive and insulative tiers, pillar structures, and selective tier configurations to enhance electrical communication and reduce horizontal footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional vertical memory array architectures are used to increase integration density, then the number of switching devices per unit die area is increased, but data transfer rates are hampered and power consumption increases
Solution Approach 1:
The memory array is segmented into multiple independent vertical stacks, each with its own digit line. This segmentation allows parallel access to multiple memory regions simultaneously, improving data transfer rates while maintaining high device density through the vertical architecture.
Solution Approach 2:
The patent transitions from planar 2D digit line arrangements to 3D vertical digit line structures that extend through multiple tiers. This dimensional change enables shorter horizontal routing distances and reduces interference between adjacent digit lines, improving both data transfer performance and power efficiency.
2Quantity of substance
If conventional vertical memory array architectures are used to increase integration density, then the number of switching devices per unit die area is increased, but feature sizes cannot be reduced further
Solution Approach 1:
The patent implements a nested structure where digit lines are embedded within the vertical stack tiers, with conductive structures positioned at multiple elevation levels. This nesting allows continuous scaling of device density without proportionally increasing feature sizes, as the vertical dimension provides additional routing space.
Solution Approach 2:
By utilizing the vertical dimension with digit lines extending through multiple tiers at different elevations, the patent achieves continued scaling of integration density without being constrained by horizontal feature size reductions alone. The 3D arrangement provides additional spatial degrees of freedom for device placement.
3Quantity of substance
If more digit lines are added to increase memory density, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The vertical stack structure serves multiple functions simultaneously: it provides memory cell storage, contains digit lines for data access, and integrates select devices for string selection. This multi-functionality allows increased memory density without proportionally increasing manufacturing complexity, as the same vertical structure fulfills multiple architectural requirements.
Solution Approach 2:
The memory array is divided into multiple independent vertical stacks that can be manufactured using similar processes. This segmentation into repeating units allows standardized fabrication techniques to be applied across the entire array, managing manufacturing complexity while achieving high overall density through parallel stack construction.
Data Source
AI summary
A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.