3D Memory Cell Stacking With Discharge Interconnection Reliability
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Solution Overview
Problem
The integration and operational reliability of semiconductor devices are limited by the area occupied by unit memory cells, prompting the development of three-dimensional semiconductor devices with stacked memory cells, but existing manufacturing methods lack stability and reliability.
Innovation Solution
A semiconductor device with a gate structure comprising alternately stacked conductive and insulating layers, channel structures penetrating the gate, and contact plugs connected to bit lines and peripheral circuits, along with a discharge interconnection for improved charge management and reliability, manufactured using a wafer bonding method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If three-dimensional stacked memory cells are implemented to improve integration density, then the area occupied by unit memory cells is reduced, but manufacturing stability and reliability deteriorate
Solution Approach 1:
The manufacturing process is divided into multiple wafers (first wafer, second wafer, third wafer) that are processed separately and then bonded together. This segmentation allows each wafer to be manufactured with standard reliability controls while achieving 3D stacking for improved integration density.
Solution Approach 2:
Multiple memory cell structures are stacked vertically by bonding wafers together, with each wafer containing complete memory cell structures. The channel structures penetrate through multiple gate structures across different wafers, creating a nested 3D configuration that reduces footprint area while maintaining manufacturing reliability through modular wafer-level fabrication.
2Ease of manufacture
If conventional manufacturing methods are used for simplicity, then ease of manufacture is maintained, but operational reliability deteriorates
Solution Approach 1:
Contact plugs are formed on the bit line before the stack is constructed. This preliminary action ensures proper electrical connection is established early in the manufacturing process, improving operational reliability while maintaining a systematic and manageable fabrication sequence.
Solution Approach 2:
A discharge interconnection structure is introduced as an intermediary component to manage charge discharge operations. This separate intermediary structure improves operational reliability by providing dedicated charge management pathways without complicating the main memory cell fabrication process.
3Reliability
If discharge interconnection structure is added to improve charge management, then operational reliability is improved, but device complexity increases
Solution Approach 1:
The discharge interconnection structure serves multiple functions: it provides charge discharge pathways, connects to peripheral circuits, and integrates with the bit line structure. By making this structure multi-functional, the patent improves operational reliability without adding excessive complexity, as the same structure performs multiple roles in the device operation.
Data Source
AI summary
A semiconductor device includes a gate structure including conductive layers and insulating layers, which are alternately stacked, channel structures penetrating the gate structure, and contact plugs disposed under the gate structure and connected to the channel structures, respectively. The semiconductor device also includes a bit line connected to the channel structures through the contact plugs, a peripheral circuit disposed under the bit line, and a discharge interconnection that connects the bit line and the peripheral circuit.