3D Memory Device Discrete Elements Airgap Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming discrete memory elements and airgap insulating layers, which affect the scalability and performance of memory stack structures.
Innovation Solution
A method involving an alternating stack of insulating layers and molybdenum layers over a substrate, with memory stack structures that include a vertical semiconductor channel and discrete tubular dielectric metal oxide spacers, a continuous silicon oxide blocking dielectric layer, and a tunneling dielectric layer, allowing for the formation of vertically spaced memory-level structures without direct contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete memory elements are formed with vertical spacing without direct contact, then data retention and isolation are improved, but manufacturing complexity increases
Solution Approach 1:
The memory film is segmented into discrete memory-level structures that are vertically spaced without direct contact. Each memory level is separated by etch-stop layers and insulating layers, creating isolated charge storage regions. This segmentation improves data retention by preventing charge leakage between levels while maintaining manufacturability through standardized layering processes.
Solution Approach 2:
Etch-stop layers are formed preliminarily between each memory level during the stacking process. These pre-formed etch-stop layers facilitate subsequent etching operations to create the discrete spaced structure. By preparing these isolation layers in advance, the manufacturing process is simplified compared to forming spacing structures after complete assembly.
2Productivity
If airgap insulating layers are used to isolate memory elements, then scalability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Etch-stop layers serve as intermediary structures between adjacent memory levels, providing a defined interface for creating airgaps. These intermediary layers control the spacing precision by establishing clear etch boundaries, allowing scalable fabrication without requiring extremely precise direct spacing between memory elements. The etch-stop layers absorb manufacturing variations and ensure consistent airgap formation.
Solution Approach 2:
The patent utilizes material parameter changes, specifically employing etch-stop layers with distinct etch selectivity compared to surrounding materials. This parameter difference enables selective removal of material to form airgaps with controlled dimensions. By changing the etch selectivity parameter rather than relying solely on geometric precision, scalable manufacturing with relaxed tolerance requirements is achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the scalability and performance of memory devices by ensuring precise spacing and isolation of memory elements, improving data retention and reducing manufacturing complexity.
Implementation Method 1
The memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures
Implementation Method 2
each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion
Data Source
AI summary
A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.