3D Memory Devices With Discrete Charge Trapping Layers
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Solution Overview
Problem
The challenge in 3D NAND flash memory devices is the degradation of performance due to the continuous charge trapping layer causing coupling and charge spreading effects, which limits vertical scale-up and increases fabrication complexity.
Innovation Solution
The implementation of discrete charge trapping layers at different levels, formed on a gate electrode with an inverted 'T' or double-sided staircase shape, mitigates the spreading effect without increasing fabrication complexity, allowing for vertical scaling of 3D memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a continuous charge trapping layer is used, then fabrication is simpler, but charge spreading and coupling effects increase causing performance degradation
Solution Approach 1:
The continuous charge trapping layer is divided into multiple discrete charge trapping layers at different vertical levels. Each discrete layer is separated by blocking layers, which prevents charge spreading between layers while maintaining individual charge storage capability. This segmentation resolves the contradiction by eliminating charge coupling effects that occur in continuous layers.
Solution Approach 2:
Blocking layers are introduced as intermediary structures between discrete charge trapping layers. These blocking layers act as mediators that prevent charge spreading and coupling between adjacent charge trapping layers, thereby improving performance without significantly complicating the fabrication process.
2Reliability
If discrete charge trapping layers are implemented, then charge spreading effects are reduced, but fabrication complexity increases
Solution Approach 1:
Multiple discrete charge trapping layers are formed using a unified fabrication approach where layers are created in sequence with similar process steps. The gate electrode structure with inverted T or double-sided staircase shape provides a common framework that simplifies the alignment and formation of multiple discrete layers, reducing overall fabrication complexity.
Solution Approach 2:
The charge trapping structure transitions from a two-dimensional continuous layer to a multi-level three-dimensional discrete structure. By utilizing the vertical dimension with multiple stacked layers at different heights, the design achieves better charge isolation while maintaining fabrication efficiency through vertical integration rather than lateral expansion.
3Ease of manufacture
If planar memory cells are scaled to smaller sizes, then manufacturing cost is reduced, but memory density approaches an upper limit
Solution Approach 1:
The memory architecture transitions from planar (2D) to three-dimensional vertical stacking. Multiple charge trapping layers are stacked vertically above the substrate, enabling memory density to increase in the vertical dimension rather than requiring further lateral scaling of planar cells. This maintains manufacturing feasibility while dramatically increasing storage capacity.
Solution Approach 2:
Multiple memory layers are nested vertically, with each discrete charge trapping layer and its associated channel layer forming a stacked memory cell structure. These nested layers are integrated around a central gate electrode, creating a compact three-dimensional memory architecture that maximizes density without requiring proportional increases in lateral footprint.
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode having a two-sided staircase shape above the substrate, a blocking layer on the gate electrode, a plurality of discrete charge trapping layers each extending laterally on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of discrete channel layers each extending laterally on the tunneling layer. The plurality of charge trapping layers are disposed corresponding to stairs of the two-sided staircase shape of the gate electrode, respectively. The plurality of channel layers are disposed corresponding to the stairs of the two-sided staircase shape, respectively.