3D Semiconductor Memory Manufacturing With Doped Channel Contacts
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in simplifying the manufacturing process due to complex structural arrangements and electrical connections between memory cells and gate stack structures.
Innovation Solution
A method involving the alternated stacking of material layers, formation of hollowed blocking and tunnel insulating layers, and creation of a channel layer with a doped contact layer to facilitate electrical connections within the semiconductor structure, including the formation of data storage patterns and protective structures to enhance manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If complex structural arrangements are used to achieve three-dimensional memory cell stacking, then storage capacity increases, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct sequential steps: forming alternating first and second material layers, creating hollowed blocking insulating layers, forming data storage patterns, creating hollowed tunnel insulating layers, forming channel layers, creating slits, and forming protective structures. This segmentation allows each step to be optimized independently while maintaining overall process manageability despite the complex three-dimensional structure being built.
Solution Approach 2:
The preliminary doped semiconductor structure is formed before the alternating material layers are stacked, establishing the foundation for subsequent processing. Additionally, the hollowed blocking insulating layers are formed to extend into the preliminary doped semiconductor structure before data storage patterns are created, preparing the structure in advance for subsequent steps and reducing overall manufacturing complexity.
2Quantity of substance
If complex structural arrangements are used to achieve three-dimensional memory cell stacking, then storage capacity increases, but production efficiency decreases
Solution Approach 1:
Multiple functions are merged into single process steps where possible. For example, the hollowed blocking insulating layer formation simultaneously creates isolation structures and prepares interfaces for data storage patterns. The alternating stacking of first and second material layers creates both structural support and electrical isolation in a single sequence, improving production efficiency while maintaining three-dimensional stacking capability.
Solution Approach 2:
The alternating first and second material layers serve multiple functions: providing structural support, creating electrical isolation, and defining regions for subsequent pattern formation. The hollowed insulating layers simultaneously provide electrical isolation and serve as templates for data storage pattern formation, reducing the total number of processing steps required.
3Quantity of substance
If complex structural arrangements are used to achieve three-dimensional memory cell stacking, then storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
Different regions of the structure are formed with different properties through selective processing. The hollowed blocking insulating layers extend to specific depths into the preliminary doped semiconductor structure, creating localized regions with different electrical and structural characteristics. Data storage patterns are formed at specific locations within the hollowed regions, allowing precise control over where electrical connections are made while maintaining overall manufacturing feasibility.
Solution Approach 2:
The preliminary doped semiconductor structure is prepared in advance with specific doping profiles and geometries that guide subsequent processing steps. The hollowed blocking insulating layers are formed to extend into predetermined regions of the preliminary structure, establishing precise geometric constraints before data storage patterns are formed, thereby reducing the precision requirements for subsequent steps.
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The manufacturing method of the semiconductor memory device includes: stacking a plurality of first material layers and a plurality of second material layers over a preliminary doped semiconductor structure; forming a blocking insulating layer, a data storage layer, a tunnel insulating layer, and a channel layer, which penetrate the plurality of first and second material layers, and extend to the inside of the preliminary doped semiconductor structure; forming a slit penetrating the plurality of first and second material layers; forming a protective structure as a double layer or a single layer on a sidewall of the slit; and forming a doped channel contact layer which penetrates a portion of the preliminary doped semiconductor structure in a direction intersecting the channel layer, and is in contact with the channel layer.