3D Memory Source-Channel Interface with Doped Conical Pedestal
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently integrating doped source-channel interface structures, which affect the performance and scalability of vertical NAND strings.
Innovation Solution
A memory device is designed with a doped source-level material layer structure comprising a lower and upper source-level semiconductor layer, a source contact layer, and a memory opening fill structure that includes a vertical semiconductor channel surrounded by a memory film and a conical source pedestal, with the conical pedestal partially doped to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source-level material layers are used in three-dimensional memory devices, then the device structure is simpler to manufacture, but the conductivity and performance of vertical NAND strings are insufficient
Solution Approach 1:
The patent applies local quality by creating a conical source pedestal with graded doping concentration at the source-channel interface. The doping concentration varies spatially within the source pedestal, with higher doping near the channel interface to enhance conductivity where it is most needed, while maintaining lower doping in other regions. This localized optimization improves overall device performance without requiring complete restructuring of the entire source-level material layers.
Solution Approach 2:
The patent employs composite materials by integrating multiple material layers with different properties at the source-channel interface. The source pedestal is formed as a composite structure combining doped semiconductor materials with varying doping concentrations, creating a multi-layered composite that optimizes both conductivity and structural integrity. This composite approach allows simultaneous achievement of high reliability and controlled complexity.
2Reliability
If doped source-channel interface structures are integrated to enhance performance, then the conductivity improves, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the doped source pedestal structure before completing the full source-level material layer integration. The conical source pedestal with optimized doping profile is prepared in advance, allowing subsequent manufacturing steps to build upon this pre-optimized foundation. This sequencing reduces the complexity of integrating doped structures into the final device, as the critical doping profile is established early in the process.
3Reliability
If the source pedestal is heavily doped to improve conductivity, then the electrical performance enhances, but the doping process complexity and precision requirements increase
Solution Approach 1:
The patent implements local quality through spatially varying doping concentration in the source pedestal. Rather than uniform heavy doping throughout, the doping concentration is optimized locally at the source-channel interface where it is most critical for conductivity. The doping profile transitions from higher concentration near the channel to lower concentration in deeper regions, achieving high electrical performance while reducing overall doping complexity and precision requirements compared to uniform heavy doping.
Data Source
AI summary
A memory device includes source-level material layers including a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and the source contact layer, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel including an intrinsic or first conductivity type semiconductor material, a memory film surrounding the vertical semiconductor channel, and a conical source pedestal in contact with the source contact layer and in contact with a bottom surface of the vertical semiconductor channel, such that at least portion of the conical source pedestal includes a second conductivity type semiconductor material.