3D Memory Array Double-Global-Bit-Line Leakage Control
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Solution Overview
Problem
Existing three-dimensional memory arrays face challenges in reducing leakage currents and manufacturing complexity due to the need for diodes and complex architectures, which affect data reading and programming efficiency and cost.
Innovation Solution
A three-dimensional memory system with a double-global-bit-line architecture and single-sided word line configuration, where local bit lines are vertically oriented and connected to global bit lines, eliminating the need for diodes and simplifying the manufacturing process, allowing for independent voltage control of adjacent bit lines to reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If diodes are added to reduce leakage currents in variable resistive memory elements, then data reading accuracy improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes diodes from the memory cell structure entirely, extracting the harmful component that caused leakage currents. Instead of adding diodes in series with each memory element, the invention uses a differential read architecture with paired bit lines that naturally cancels leakage currents through voltage differential measurement, achieving accurate reading without the complexity of diode-based solutions
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components that detect voltage differentials between paired bit lines. These sense amplifiers mediate the reading process by comparing voltages from two bit lines simultaneously, allowing the system to distinguish actual data signals from leakage currents without requiring diodes at each memory element
2Reliability
If diodes are added to reduce leakage currents, then reliability improves, but ease of manufacture deteriorates
Solution Approach 1:
The patent extracts diodes from the memory cell structure, simplifying the manufacturing process. By eliminating the need to fabricate and integrate diodes with each memory element, the invention reduces manufacturing steps, lowers costs, and improves yield while maintaining reliability through the differential read architecture that compensates for leakage currents at the circuit level rather than requiring component-level protection
3Measurement precision
If complex architectures are used to reduce leakage currents, then data reading accuracy improves, but productivity deteriorates
Solution Approach 1:
The patent segments the bit line structure into pairs of local bit lines (BL0, BL1) that are differentially coupled to memory elements. This segmentation allows parallel reading operations across multiple bit line pairs simultaneously, improving productivity while maintaining accuracy through the differential measurement approach that eliminates leakage current interference
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture significantly reduces leakage currents, enhances data reading accuracy, and lowers manufacturing costs by simplifying the process and eliminating the need for diodes, while maintaining high storage density and efficiency.
Implementation Method 1
Another type of re-programmable non-volatile memory cell uses variable resistance memory elements that may be set to either conductive or non-conductive states (or, alternately, low or high resistance states, respectively)
Data Source
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AI summary
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A double-global-bit-line architecture provides a pair of global bit lines for each bit lines for accessing a row of memory elements in parallel. A first one of each pair allows the local bit lines of the row to be sensed while a second one of each pair allows local bit lines in an adjacent row to be set to a definite voltage so as to eliminate leakage currents between adjacent rows of local bit lines.