3D Memory Array Double Patterning for Stable High-Density Word Lines
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high memory cell density while preventing structural instability due to high aspect ratios during the formation of word lines and transistors, leading to issues such as twisting or collapsing of features.
Innovation Solution
A multiple-patterning process is employed to form word lines and transistors, specifically using a double patterning process to pattern first and second trenches in a multilayer stack, followed by forming conductive features and ferroelectric strips to create a ferroelectric random access memory (FERAM) array, which improves the aspect ratio and prevents structural instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single-patterning process is used to form word lines and transistors, then manufacturing process is simple, but aspect ratio becomes too high causing structural instability
Solution Approach 1:
The patent applies segmentation by dividing the single patterning step into multiple patterning steps (double patterning process). First trenches are formed and filled with conductive material, then second trenches are formed and filled with conductive material to form word lines. This segmentation allows each trench to have a lower aspect ratio than a single deep trench would require, preventing structural instability while maintaining manufacturing feasibility.
2Quantity of substance
If memory cell density is increased, then storage capacity improves, but structural stability deteriorates due to higher aspect ratios
Solution Approach 1:
The patent transitions from a single-dimension deep trench approach to a multi-dimensional approach by forming trenches in a multilayer stack with alternating dielectric and sacrificial layers. This dimensional change allows the formation of word lines and transistors with optimized aspect ratios while achieving high memory cell density through the stacked architecture.
3Stability of the object's composition
If aspect ratio is reduced to prevent twisting and collapsing, then structural stability improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by first forming the multilayer stack with alternating dielectric and sacrificial layers before forming the trenches. The sacrificial layers are removed to create spaces that guide subsequent conductive material deposition. This preliminary structuring simplifies the overall process by pre-defining the final word line and transistor positions, reducing the complexity that would otherwise arise from trying to directly form low aspect ratio structures.
Data Source
AI summary
In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.