3D Memory On-Axis Self-Aligned Drain-Select Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving effective self-aligned drain-select-level isolation structures, which are crucial for enhancing memory density and performance but are difficult to manufacture with existing methods.
Innovation Solution
A three-dimensional memory device is developed with on-axis self-aligned drain-select-level isolation structures, achieved through an alternating stack of insulating and electrically conductive layers, where memory openings are formed, and a multi-pillared dielectric isolation structure is created by depositing dielectric material in laterally-extending cavities and discrete corner cavities, allowing for precise lateral separation of conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used for three-dimensional memory devices, then existing fabrication processes can be maintained, but effective self-aligned drain-select-level isolation structures cannot be achieved
Solution Approach 1:
The patent performs preliminary actions by forming the alternating stack of insulating and conductive layers with pre-defined patterns before creating the memory openings. The dielectric isolation structures are formed in advance within the stack, establishing self-alignment references that guide subsequent processing steps, thereby achieving precise isolation structure alignment without requiring complex post-processing adjustments
Solution Approach 2:
The patent implements nesting by placing multiple functional layers within each other in a hierarchical structure. The dielectric isolation structures are nested within the alternating stack of insulating and conductive layers, with memory openings penetrating through these nested layers. This nested configuration enables self-alignment where inner structures automatically reference outer structures, resolving the alignment precision issue while maintaining fabrication feasibility
2Quantity of substance
If memory density is increased through three-dimensional vertical NAND strings, then storage capacity improves, but manufacturing difficulty increases
Solution Approach 1:
The patent segments the memory device into distinct functional components: alternating insulating and conductive layers form separate functional zones, memory openings create discrete vertical channels, and dielectric isolation structures divide the conductive layers into isolated segments. This segmentation enables high memory density through vertical stacking while simplifying manufacturing by allowing each segment to be formed using standardized, repeatable processes
Solution Approach 2:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical NAND strings by stacking multiple layers vertically. The alternating insulating and conductive layers are arranged in the vertical dimension, creating high-density storage without increasing lateral footprint. This dimensional change increases memory capacity while the self-aligned formation methods maintain manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient self-aligned isolation structures, improving memory density and performance by effectively separating electrically conductive layers, thereby enhancing the overall functionality of the memory device.
Implementation Method 1
forming a multi-pillared dielectric isolation structure by depositing a dielectric material in volumes of the at least one laterally-extending cavity and in the discrete corner cavities
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures located within a respective one of the memory openings. A multi-pillared dielectric isolation structure extends through upper sections of a neighboring pair of memory openings. The multi-pillared dielectric isolation structure includes a plurality of dielectric pillar portions located within a respective one of the memory openings, and at least one horizontally-extending portion adjoining each of the plurality of dielectric pillar portions and located between a vertically neighboring pair of insulating layers within the alternating stack. The at least one horizontally-extending portion laterally separates laterally neighboring strips of at least one electrically conductive layer within the alternating stack.