3D Memory Device Drain Select Isolation Without Etch Stop
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Solution Overview
Problem
The existing methods for forming gapless lithographic pitch alignment (GLPA) structures in three-dimensional memory devices require an aluminum oxide etch stop layer, which is challenging due to difficulties in patterning aluminum oxide and simultaneous anisotropic etching of silicon oxide and silicon nitride, making the process complex and inefficient.
Innovation Solution
A method for forming GLPA structures without using a metal oxide etch stop layer, involving the formation of an alternating stack of insulating and spacer material layers, memory opening fill structures, and drain-select-level pillar structures that are electrically connected to memory-level semiconductor channels, with a planar insulating spacer layer contacting the memory films and drain-select-level gate electrodes, simplifying the etching process and eliminating the need for an etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an aluminum oxide etch stop layer is used to form GLPA structures, then the vertical separation and electrical isolation are improved, but the manufacturing complexity and process difficulty increase significantly
Solution Approach 1:
The patent removes the aluminum oxide etch stop layer from the GLPA structure formation process. Instead of using a separate etch stop layer, the invention uses the planar insulating spacer layer that is already present in the device structure to provide both the spacing and the etch stop function, thereby eliminating an unnecessary component and simplifying the manufacturing process.
Solution Approach 2:
The planar insulating spacer layer is designed to serve multiple functions simultaneously: it provides the required vertical separation distance, acts as an etch stop layer during subsequent processing, and maintains electrical isolation between conductive layers. This multi-functional approach eliminates the need for a dedicated etch stop layer.
2Productivity
If simultaneous anisotropic etching of silicon oxide and silicon nitride is performed, then the GLPA structure formation is achieved, but the etching process control and precision are compromised
Solution Approach 1:
The patent divides the etching process into separate sequential steps rather than attempting simultaneous anisotropic etching of multiple materials. First, silicon oxide is etched, then silicon nitride is etched in a subsequent step. This segmentation allows each etching step to be optimized for its specific material, improving both precision and control.
3Manufacturing precision
If a metal oxide etch stop layer is used, then the etching selectivity is improved, but the patterning difficulty and process steps increase
Solution Approach 1:
The patent replaces the expensive and difficult-to-pattern metal oxide etch stop layer with a planar insulating spacer layer that is already part of the device structure. This spacer layer serves as a temporary etch stop during the GLPA formation process and is later removed or integrated into the final structure, eliminating the need for separate etch stop layer deposition and patterning steps.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective memory-level semiconductor channel and a respective memory film. Drain-select-level gate electrodes overlie the alternating stack. Drain-select-level pillar structures extend through a respective one of the drain-select-level gate electrodes. Each drain-select-level semiconductor channel is electrically connected to an underlying one of the memory-level semiconductor channels. A planar insulating spacer layer having a homogeneous composition throughout directly contacts top surfaces of the memory films and bottom surfaces of the drain-select-level gate electrodes.