3D Memory Drain Select Transistors via Segmented Gates
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Solution Overview
Problem
Current methods for forming three-dimensional memory devices with separately formed drain side select transistors are inefficient, as they lack a systematic approach to integrate drain select level structures effectively, leading to suboptimal performance and density in NAND string memory arrays.
Innovation Solution
A method involving the formation of an alternating stack of insulating and spacer material layers over a substrate, followed by the creation of memory openings and memory stack structures, with subsequent formation of drain select level dielectric layers and conductive layers, allowing for lateral recesses and conductive lines that extend horizontally and are spaced apart, enabling efficient integration of drain select level gate dielectrics and channel portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to form three-dimensional memory devices, then the manufacturing process is simpler, but the density and performance of the memory device are suboptimal
Solution Approach 1:
The drain select transistor gate is divided into multiple segments positioned at different heights within the memory opening. This segmentation allows each gate segment to independently control different portions of the channel, improving device performance and density without requiring complete redesign of the entire memory structure.
Solution Approach 2:
The patent introduces vertical positioning of multiple drain select gates at different heights within the same memory opening, adding a vertical dimension to the gate structure. This enables more efficient space utilization and improved device characteristics without increasing lateral footprint.
2Reliability
If drain select level structures are not systematically integrated, then the manufacturing process is less complex, but the selectivity and operational efficiency are reduced
Solution Approach 1:
The method forms a complete alternating stack of insulating and spacer material layers before creating memory openings and integrating drain select structures. This preliminary formation of the alternating stack provides a systematic framework that guides subsequent processing steps, improving selectivity while maintaining manufacturing feasibility through structured sequencing.
Solution Approach 2:
The patent applies different material properties and structural configurations to specific regions: insulating layers in certain positions, conductive spacer layers in others, and selectively positioned drain select gates. This local differentiation of material and structural qualities enables improved selectivity and operational efficiency without requiring complete restructuring of the entire device.
Data Source
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AI summary
Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.