3D Memory Drain-Select Via Layout for Multilevel Connectivity
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in effectively connecting multiple drain-select-level electrically conductive layers located at different levels, which affects the performance and efficiency of memory operations.
Innovation Solution
The implementation of drain-select-level contact via structures that directly connect vertically spaced apart drain-select-level electrically conductive layers, along with methods to form these structures by alternating stacks of insulating and sacrificial material layers, followed by replacement with conductive layers and isolation structures, ensuring electrical connectivity across different levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple drain-select-level electrically conductive layers are vertically spaced apart to enable three-dimensional memory structure, then memory density and capacity are improved, but electrical connectivity and operational efficiency deteriorate
Solution Approach 1:
The patent segments the drain-select-level electrically conductive layers into multiple vertically spaced apart layers (first drain-select-level electrically conductive layer, second drain-select-level electrically conductive layer, etc.), allowing each layer to be independently formed and controlled while maintaining overall electrical connectivity through the vertical stacking architecture
Solution Approach 2:
The patent transitions from two-dimensional planar connections to three-dimensional vertical connections by stacking multiple drain-select-level electrically conductive layers vertically, enabling memory density improvement while maintaining electrical connectivity through the vertical dimension rather than horizontal expansion
2Quantity of substance
If vertically spaced apart drain-select-level electrically conductive layers are implemented, then memory device capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by first forming the alternating stack of insulating layers and sacrificial material layers, then using these sacrificial layers as templates to guide the subsequent formation of drain-select-level electrically conductive layers at specific vertical positions, simplifying the overall manufacturing process
Solution Approach 2:
The patent uses sacrificial material layers as intermediary structures during manufacturing, which are temporarily formed to define the positions of drain-select-level electrically conductive layers, then removed and replaced with the final conductive materials, simplifying the fabrication process
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers located above the word-line-level electrically conductive layers, memory opening fill structures vertically extending through the alternating stack, and drain-select-level contact via structures. A first one of the drain-select level contact structures directly contacts at least a first two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other. A second one of the drain-select level contact structures directly contacts at least a second two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other and which are located below the at least the first two of the drain-select-level electrically conductive layers.