3D Vertical Memory Digit-Line Driver Layout for Routing Relief
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Solution Overview
Problem
Existing memory devices with 3D vertical structures face challenges in optimizing the use of space under the memory array for circuitry, leading to routing congestion and limited driving capability of digit lines.
Innovation Solution
The memory device incorporates a digit line driver with thin film transistors positioned in a second area outside the active memory cell area, allowing the digit line to extend partially into this area, and includes a driver comprising multiple thin film transistors and pillars to enhance driving capability and reduce routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If decoding circuitry is formed in the substrate under the 3D array of memory cells, then the space available for placing other circuitry is reduced, but the memory cell density is increased
Solution Approach 1:
The patent extends the digit line from the first area (under the memory array) into a second area outside the memory array. This spatial extension into an additional dimension allows the driver circuitry to be positioned in the second area, thereby increasing the area available for placing circuitry while maintaining the high-density 3D memory array structure.
2Device complexity
If the digit line is confined to the first area under the memory array, then the routing is simplified, but the driving capability is limited
Solution Approach 1:
The digit line is configured to extend from the first area into a second area outside the memory array. This extension provides additional spatial freedom for routing the digit line with adequate width and spacing, thereby improving driving capability while maintaining manageable routing complexity through systematic extension.
Solution Approach 2:
The patent divides the digit line into segments: a first portion in the first area under the memory array and a second portion extending into the second area. This segmentation allows different portions of the digit line to serve different functions - the first portion for compact integration and the second portion for enhanced driving capability and connection to driver circuitry.
3Area of moving object
If all circuitry is placed under the memory array, then the device area is minimized, but the routing congestion increases
Solution Approach 1:
The patent utilizes a second area outside the memory array for extending the digit line and placing driver circuitry. This approach maintains minimal device area by keeping the memory array compact while relocating circuitry to an adjacent area, thereby reducing routing congestion without significantly increasing overall device footprint.
Data Source
AI summary
It is disclosed a memory device comprising: a plurality of pillars extending through a plurality of levels of a memory array; one or more memory cells of the memory array coupled with a respective pillar and a respective word line at each level; a digit line; a plurality of TFTs, each TFT being configured to selectively couple the digit line with a respective pillar, wherein the plurality of pillars, the one or more memory cells and the plurality of thin film transistors are positioned in a first area of the memory array, and wherein the digit line extends in the first area and at least partially in a second area outside the first area; a driver for the digit line. The driver comprises a first TFT, a second TFT and a pillar, wherein the first TFT, the second TFT and the pillar are positioned in the second area.