3D Memory Sub-Word Line Drivers for Layer-to-Layer Speed Matching
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Solution Overview
Problem
Three-dimensional integrated circuit memory devices face performance deterioration due to varying electrical characteristics of vertically stacked word lines, leading to operational inefficiencies.
Innovation Solution
Implementing sub-word line drivers with distinct driving characteristics for each layer, adjusting driving voltages, timings, and transistor channel widths to match the electrical characteristics of electrodes in different layers, thereby maintaining consistent performance across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple layers are vertically stacked to increase integration density, then the degree of integration is improved, but performance deterioration occurs due to varying electrical characteristics of word lines in different layers
Solution Approach 1:
The patent applies local quality by configuring sub-word line drivers with different driving characteristics for different layers. Specifically, sub-word line drivers for lower layers are designed with stronger driving capability (larger transistor channel widths) to compensate for the higher capacitance and slower response of lower layers, while upper layers use weaker driving characteristics. This localized adaptation ensures uniform access time and performance across all layers despite their different electrical characteristics.
2Reliability
If sub-word line drivers with different driving characteristics are implemented for each layer, then performance consistency is improved, but device complexity increases
Solution Approach 1:
The patent segments the word line driver into multiple sub-word line drivers, each responsible for driving word lines in specific layers. This segmentation allows each sub-driver to be independently optimized for its target layer's electrical characteristics. The drivers are organized in groups where each group handles a specific range of layers, and the channel widths of transistors in each sub-driver are specifically designed to match the capacitance and response characteristics of those layers.
3Speed
If transistor channel widths are adjusted to match electrical characteristics of different layers, then operating speed consistency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the physical parameters of the sub-word line drivers, specifically the channel widths of transistors, to match the electrical characteristics of different layers. Lower layer sub-drivers use larger channel widths to provide stronger driving current for the higher capacitance of lower layers, while upper layer sub-drivers use smaller channel widths. This parameter adjustment compensates for the varying electrical characteristics and achieves uniform access time across all layers.
Data Source
AI summary
A three-dimensional integrated circuit memory device includes a substrate having layers vertically stacked thereon; the layers include: memory cells horizontally arranged to form one row, a word line electrically connected to the plurality of memory cells, and an electrode horizontally extending from the word line and forming a stair structure with other electrodes associated with respective ones of the plurality of layers. Vertically-extending contacts are provided, which electrically contact corresponding electrodes in an open area of each of the layers. A first sub-word line driver has a first driving characteristic and is electrically connected through a first one of the vertically-extending contacts to an electrode associated with a first layer layers. A second sub-word line driver has a second driving characteristic different from the first driving characteristic and is electrically connected through a second one of the vertically-extending contacts to an electrode associated with a second layer among the layers.