3D Memory Devices with Variable Drain Select Gate Cut
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, leading to density constraints, which 3D memory architecture aims to address by increasing memory density through vertical memory strings and innovative DSG cut designs.
Innovation Solution
The 3D memory device design includes a memory stack with interleaved conductive and dielectric layers, featuring drain select gate (DSG) lines that control memory strings, with varying numbers of DSG lines in different regions to avoid dummy memory strings and improve electrical performance, and a method for forming these devices involves forming sacrificial layers, replacing them with conductive layers, and creating specific channel structures and plugs to achieve uniform height and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is pursued, then memory density increases, but fabrication complexity and cost increase beyond acceptable limits
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by forming vertical memory strings extending through stacked conductive and dielectric layers. This dimensional change enables continued memory density improvement without requiring further scaling of planar feature sizes, thereby avoiding the associated fabrication complexity and cost increases
2Ease of manufacture
If uniform memory strings are formed across all regions, then manufacturing simplicity is maintained, but electrical performance deteriorates due to dummy memory strings
Solution Approach 1:
The patent applies different numbers of drain select gate (DSG) lines to different regions of the memory stack. Specifically, first regions contain memory strings with a first number of DSG lines while second regions contain memory strings with a second number of DSG lines. This local differentiation eliminates dummy memory strings in certain regions, improving electrical performance and reliability while maintaining manufacturing simplicity through a systematic regional design approach
3Reliability
If DSG lines are increased in all regions, then electrical performance improves, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent optimizes electrical performance by selectively increasing the number of DSG lines only in specific regions where it is most beneficial, rather than uniformly across the entire memory device. This localized approach improves electrical performance in critical areas while avoiding unnecessary complexity in regions where fewer DSG lines suffice
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each memory string extends vertically through the memory stack. The plurality of memory strings are divided into a plurality of regions of the memory stack in a plan view. The conductive layers include one or more drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The numbers of the DSG lines are different among the plurality of regions. Each of the plurality of memory strings has a nominally same height.