3D Semiconductor Memory With Dual-Grain Metal Gates
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Solution Overview
Problem
The challenge lies in achieving high reliability and cost-effective mass production of three-dimensional semiconductor memory devices, which face manufacturing obstacles in maintaining or exceeding the operational reliability of their two-dimensional counterparts while increasing integration density.
Innovation Solution
The semiconductor memory device design includes stacks with gate electrodes and insulating patterns on a substrate, featuring a vertical channel and separation pattern, with specific metal patterns having different grain sizes and thicknesses to optimize structure and reliability, and an insulating layer covering the metal patterns for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If three-dimensional semiconductor memory devices are designed to increase integration density, then the area occupied by unit memory cells is reduced, but manufacturing obstacles increase and operational reliability becomes difficult to maintain
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked vertically with gate electrodes and insulating patterns arranged in three dimensions, enabling increased integration density while maintaining manufacturability and reliability through controlled vertical stacking and separation patterns.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing gate electrodes, insulating patterns, and separation patterns. This segmentation allows independent fabrication and quality control of each layer, facilitating mass production while maintaining operational reliability.
2Ease of manufacture
If three-dimensional semiconductor memory devices are designed for mass production at low cost, then manufacturing complexity increases, but maintaining high reliability becomes difficult
Solution Approach 1:
The patent employs two-tone metal patterns with different grain sizes (first and second grain sizes) within the same metal layer. This parameter variation optimizes electrical properties and stress distribution, enhancing device reliability while using standard fabrication processes for cost-effective mass production.
Solution Approach 2:
Different regions of the metal patterns have different grain sizes tailored to local requirements. Areas requiring higher conductivity have different grain characteristics than areas requiring stress management, allowing optimized performance throughout the device without increasing overall manufacturing complexity.
Data Source
AI summary
Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.