3D Memory Array Bonding With Dual-Level Peripheral Circuits
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Solution Overview
Problem
Existing semiconductor technologies face challenges in efficiently integrating three-dimensional memory arrays with peripheral circuits, leading to complexities in manufacturing and increased costs.
Innovation Solution
A bonded assembly comprising a memory die and a logic die, with a backside peripheral circuit, is proposed. The memory die includes a three-dimensional memory array, memory-side dielectric material layers, and metal interconnect structures, while the logic die features a logic-side peripheral circuit and bonding pads. The backside peripheral circuit is electrically connected to the memory array, allowing for independent control of the memory array operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If three-dimensional memory arrays are integrated with peripheral circuits using conventional methods, then functional capability is achieved, but manufacturing complexity increases and costs rise
Solution Approach 1:
The device is divided into separate memory die and logic die components, each performing distinct functions. The memory die contains the three-dimensional memory array while the logic die contains the peripheral circuits, allowing independent fabrication and optimization of each component before bonding them together.
Solution Approach 2:
The peripheral circuits are moved from the traditional planar integration approach to a three-dimensional stacked configuration. By bonding the logic die to the memory die vertically, the patent utilizes the vertical dimension to achieve integration without increasing lateral footprint or manufacturing process complexity.
2Device complexity
If conventional integration methods are used, then electrical connection is established, but lateral wiring complexity and metallic via structures increase
Solution Approach 1:
The patent eliminates the need for complex lateral wiring and metallic via structures by extracting the connection function to simple bonding interfaces between dies. The bonding pads on each die provide direct electrical connection points, removing the intermediary wiring layers required in conventional integrated structures.
Solution Approach 2:
Bonding pads serve as intermediary elements that facilitate electrical connection between the memory die and logic die. These bonding pads are strategically positioned and sized to provide reliable electrical contact while simplifying the bonding process and reducing the need for additional interconnect structures.
Data Source
AI summary
A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.