3D Memory Array Bonding With Dual-Level Peripheral Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in forming efficient three-dimensional memory devices with enhanced drive current, particularly in integrating logic and memory dies with effective peripheral circuits for controlling electrical nodes in a compact and high-performance manner.
Innovation Solution
A bonded assembly is formed by integrating a memory die with a three-dimensional memory array and a logic die, where a first peripheral circuit on the logic die controls one set of electrical nodes, and a second peripheral circuit, located at a different vertical level, controls another set, utilizing doped semiconductor material layers, dielectric material layers, and metal interconnect structures for efficient electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single peripheral circuit is used to control electrical nodes in three-dimensional memory, then device complexity is reduced, but drive current and control efficiency are insufficient
Solution Approach 1:
The patent transitions from a planar single-level peripheral circuit configuration to a three-dimensional dual-level configuration. The first peripheral circuit is positioned at a first vertical level and the second peripheral circuit at a second vertical level, enabling independent control of different electrical node sets (first bit lines and second bit lines) with enhanced drive current capability while maintaining compact integration.
2Productivity
If logic die and memory die are integrated in a bonded assembly, then manufacturing efficiency is improved, but integration complexity increases
Solution Approach 1:
The patent merges the logic die and memory die into a single bonded assembly, where the logic die containing peripheral circuits is bonded to the memory die containing the three-dimensional memory array. This integration enables coordinated control of memory operations with enhanced drive current capability while improving manufacturing efficiency through unified device fabrication.
Data Source
AI summary
A bonded assembly includes a memory die containing a three-dimensional memory array, a first logic die bonded to the memory die, a first peripheral circuit located in the logic die and configured to control operation of a first set of electrical nodes of the three-dimensional memory array, and a second peripheral circuit configured to control operation of a second set of electrical nodes of the three-dimensional memory array, where the second peripheral circuit is located at a different vertical level than the first peripheral circuit relative to the three-dimensional-memory array.