3D Memory Channel Structure With Dual-Phase Doped Semiconductor Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increase in the number of memory cells stacked in three-dimensional semiconductor memory devices leads to deterioration of operating reliability.
Innovation Solution
A semiconductor memory device with a doped semiconductor layer having crystalline and amorphous areas, a channel layer passing through interlayer insulating layers, and a memory layer between conductive patterns, along with a manufacturing method involving excimer laser annealing to improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory cells stacked in three-dimensional semiconductor memory devices is increased to improve degree of integration, then the degree of integration is improved, but the operating reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct crystalline and amorphous regions within the doped semiconductor layer. The crystalline region provides stable electrical characteristics while the amorphous region controls surface roughness, allowing each area to fulfill specific functional requirements that collectively resolve the reliability-integration contradiction
Solution Approach 2:
The patent changes the physical and chemical parameters of the semiconductor layer by controlling the crystallization process through excimer laser annealing. By adjusting laser energy density, pulse duration, and temperature parameters, the patent creates a dual-phase structure that maintains electrical stability while controlling surface morphology, thereby improving operating reliability in high-density 3D memory devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the operating reliability of three-dimensional semiconductor memory devices by maintaining electrical characteristics and reducing surface roughness through controlled impurity diffusion.
Implementation Method 1
forming a doped semiconductor layer including a crystalline area and an amorphous area between the crystalline area and the first interlayer insulating layer by crystallizing a surface of the amorphous doped semiconductor layer
Implementation Method 2
crystallizing a surface of the amorphous doped semiconductor layer
Implementation Method 3
diffusing impurities in the doped semiconductor layer into the channel layer
Data Source
AI summary
A semiconductor memory device includes a plurality of conductive patterns and a plurality of second interlayer insulating layers arranged alternately with each other under a first interlayer insulating layer. The semiconductor memory device also includes a doped semiconductor layer including an amorphous area overlapping the first interlayer insulating layer and a crystalline area overlapping the first interlayer insulating layer with the amorphous area interposed between the first interlayer insulating layer and the crystalline area. The semiconductor memory device further includes a channel layer contacting the doped semiconductor layer and passing through the first interlayer insulating layer, the plurality of second interlayer insulating layers, and the plurality of conductive patterns. The semiconductor memory device additionally includes a memory layer between each of the conductive patterns and the channel layer.