3D Memory Cell Dual-Side Contacts for Higher Density Arrays
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, limiting memory density, while 3D memory architecture is needed to address these limitations by increasing storage capacity without increasing vertical space.
Innovation Solution
The method involves forming contact structures that penetrate through both surfaces of a stack structure with alternating layers and dielectric layers, allowing for increased density by extending contact structures through the 3D memory device, enabling a denser array of memory structures and higher storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density increases, but fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The memory array is arranged in a 3D stack structure with alternating conductive and dielectric layers, allowing memory density to increase vertically rather than requiring further scaling of planar features. This dimensional change resolves the fabrication challenges associated with sub-limits planar scaling while achieving higher memory density.
2Quantity of substance
If 3D memory architecture is used to address density limitation, then storage capacity increases, but device structure becomes more complex
Solution Approach 1:
The 3D memory structure is segmented into alternating conductive layers and dielectric layers, with each layer serving specific functions. Contact structures are formed to access different portions of the memory array through the stacked layers. This segmentation allows for systematic organization of memory cells in three dimensions while maintaining manageable structural complexity through repeated unit cell patterns.
Solution Approach 2:
The stack structure with alternating conductive and dielectric layers serves multiple functions simultaneously: it provides the memory array structure, creates electrical isolation between different memory cell layers, and establishes a pattern that can be accessed from multiple surfaces. This multi-functional design increases storage capacity without proportionally increasing structural complexity.
3Quantity of substance
If contact structures are formed on both surfaces of the stack structure, then overall density increases, but fabrication process becomes more complex
Solution Approach 1:
The patent forms contact structures on both the first and second opposite surfaces of the stack structure, utilizing the third dimension (vertical depth) to maximize contact structure placement. This approach allows memory array portions to be accessed from both surfaces, effectively doubling the contact interface area and increasing overall device density without requiring excessive lateral space.
Solution Approach 2:
The fabrication process merges the formation of contact structures on both surfaces into a coordinated process sequence. First contact structures are formed penetrating from the first surface, then second contact structures are formed penetrating from the second surface. This combined approach achieves maximum density while managing fabrication complexity through systematic process integration.
Data Source
AI summary
Disclosed herein is a memory device that includes a stack structure. The stack structure has alternating first layers and dielectric layers. The stack structure has a first surface and a second surface opposite to the first surface. First contact structures include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.