3D Memory Peripheral Circuit Layout Using Dual-Sided Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3-dimensional nonvolatile memory devices face challenges in achieving lightness, thinness, simplification, and high integration due to limitations in circuit design and layout.
Innovation Solution
A semiconductor device design featuring a cell area with gate electrodes, channel structures, and contact plugs, along with peripheral circuit areas on both sides of a substrate, connected via through electrodes, allowing for a chip-to-chip structure and enhanced wiring interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If peripheral circuits are integrated on the same substrate as the cell area, then device complexity is reduced, but chip area increases
Solution Approach 1:
The patent places peripheral circuit areas on both the front surface and back surface of the substrate, utilizing the third dimension (depth/thickness) to distribute circuits spatially. This allows peripheral circuits to be integrated without increasing the planar chip area, as circuits are arranged in multiple layers/surfaces rather than spreading out in a single plane.
Solution Approach 2:
The substrate is divided into distinct front and back surfaces, with different functional areas allocated to each. The cell area is positioned on the front surface while peripheral circuits are distributed across both surfaces, creating a segmented spatial organization that reduces overall chip footprint while maintaining integration.
2Reliability
If more bonding pads are placed on the substrate surface, then electrical connections improve, but chip area increases
Solution Approach 1:
Bonding pads are distributed across both the front and back surfaces of the substrate, effectively utilizing the vertical dimension to increase the total number of available bonding pads without expanding the planar chip area. This spatial distribution allows for enhanced electrical connectivity while maintaining compact dimensions.
3Productivity
If chip size is reduced for miniaturization, then productivity improves, but wiring interconnection complexity increases
Solution Approach 1:
By distributing circuits and bonding pads across multiple surfaces (front and back), the patent reduces the planar footprint of the chip while maintaining adequate wiring interconnection capacity. The multi-surface arrangement provides additional routing paths and connection points that would otherwise require larger planar space, thus enabling miniaturization without proportionally increasing wiring complexity.
Data Source
AI summary
A semiconductor device including a cell area including a first substrate, gate electrodes on the first substrate, a channel structure extending through the gate electrodes, cell contact plugs, a through contact plug, and first bonding pads, the first peripheral circuit area including second bonding pads on the first bonding pads; a second peripheral circuit area connected to the first peripheral circuit area; and a second substrate between the first peripheral circuit area and the second peripheral circuit area, the second substrate including a first surface in the first peripheral circuit area and a second surface in the second peripheral circuit area, wherein the second peripheral circuit area includes a device on the second surface, and a through electrode extending vertically through the second substrate and connected to the first peripheral circuit area.