3D Memory Cell Structure With Dual-Type Common Source Layer
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Solution Overview
Problem
The integration of 2-dimensional semiconductor devices is limited due to the high cost and complexity of fine pattern formation technology, necessitating the development of 3-dimensional semiconductor memory devices.
Innovation Solution
A semiconductor device with a peripheral circuit structure and a cell structure stacked on top, featuring gate electrodes spaced apart in a vertical direction, a channel structure extending through the gate electrodes, and a common source layer with alternating regions of different conductivity types, enhancing electrical properties and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2-dimensional planar semiconductor devices are used to increase integration, then data storage capacity increases, but the degree of integration is limited due to area constraints and fine pattern formation requirements
Solution Approach 1:
The patent transitions from 2-dimensional planar semiconductor devices to 3-dimensional vertically stacked memory cells. The cell structure includes multiple layers stacked in the vertical direction, with gate electrodes, channel structures, and source/drain regions arranged vertically to achieve higher integration density without requiring finer lateral patterning.
Solution Approach 2:
The memory device is divided into distinct functional layers including cell regions, connection regions, and peripheral circuit regions. Each layer performs specific functions and is stacked vertically, allowing independent optimization of each segment while achieving high overall integration.
2Quantity of substance
If 3-dimensional semiconductor memory devices are proposed to overcome integration limits, then degree of integration increases, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The channel structure is formed to extend through the gate electrodes before the gate electrodes are fully formed. This preliminary formation of the channel structure simplifies subsequent processing steps and enables better control over the vertical alignment and dimensions of the memory cells.
Solution Approach 2:
The patent employs alternating conductivity type impurity regions within the source/drain structures to optimize electrical properties. By changing the impurity concentration and conductivity type in different vertical regions, the device achieves better charge control and reduced leakage while maintaining manufacturability.
3Reliability
If common source layer with alternating conductivity regions is implemented, then electrical properties and reliability improve, but device structure complexity increases
Solution Approach 1:
The common source layer is divided into multiple regions with different conductivity types (first conductivity type and second conductivity type) to provide different local functions. The first regions provide one electrical function while the second regions provide another, optimizing overall device performance through spatially varying material properties.
Data Source
AI summary
A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure. The cell structure includes a plurality of gate electrodes spaced apart from each other in a vertical direction, a channel structure passing through the plurality of gate electrodes and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end, and a common source layer covering the second end of the channel structure. The channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region that contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.