3D Memory Cell Word Line with Dual Work Functions for Low Power
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by the cost and complexity of fine-pattern fabrication, prompting the need for three-dimensional semiconductor memory devices with higher integration capabilities.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a dual work function electrode structure, including a low work function electrode and a high work function electrode, separated by a dipole inducing layer, which increases cell threshold voltage and reduces power consumption while maintaining refresh characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine-pattern fabrication to increase integration density, then integration degree increases, but fabrication cost and complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell layout to three-dimensional vertically stacked architecture. Memory cells are arranged in multiple layers with bit lines extending vertically, allowing integration density to increase without requiring proportionally finer lateral patterning, thus reducing fabrication complexity while maintaining high density
2Use of energy by moving object
If conventional word line structures are used, then device simplicity is maintained, but power consumption increases and refresh characteristics deteriorate
Solution Approach 1:
The word line structure employs different work function materials at different locations: a first work function material at the end adjacent to the bit line and a second work function material at the end adjacent to the capacitor. This local differentiation optimizes electrical characteristics for each function, reducing power consumption and improving refresh characteristics without requiring complete structural redesign
Solution Approach 2:
The word line is constructed as a composite structure with multiple materials having different work functions. This composite approach allows simultaneous optimization of different functional regions of the word line, achieving lower power consumption and better refresh characteristics while maintaining structural integrity
3Reliability
If channel doping or increased channel concentration is used to adjust cell threshold voltage, then threshold voltage control is achieved, but parasitic capacitance increases and integration density decreases
Solution Approach 1:
A dipole inducing layer is introduced as an intermediary element between the gate dielectric layer and the word line. This dipole layer adjusts the flat-band voltage and threshold voltage through dipole moments without requiring channel doping or increased channel concentration, thereby maintaining integration density while achieving reliable threshold voltage control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances memory cell integration density, reduces parasitic capacitance, and achieves low power consumption by adjusting the cell threshold voltage through the flat-band shift, without the need for channel doping or increased channel concentration.
Implementation Method 1
a dipole inducing layer disposed between the high work function electrode and the gate dielectric layer
Data Source
AI summary
Present invention relates to a highly-integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, a semiconductor device comprises: an active layer including a channel, the active layer being spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed over the active layer; a word line laterally oriented in a direction crossing the active layer over the gate dielectric layer and including a low work function electrode and a high work function electrode, the high work function electrode having a higher work function than the low work function electrode; and a dipole inducing layer disposed between the high work function electrode and the gate dielectric layer.