3D Memory Cell Word Line With Dual Work Functions
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Solution Overview
Problem
The integration degree of two-dimensional semiconductor memory devices is limited by the cost and complexity of fine-pattern fabrication, necessitating the development of three-dimensional semiconductor memory devices with higher integration density.
Innovation Solution
A semiconductor device with a 3D structure featuring a dual work function electrode configuration, including a low work function electrode and a high work function electrode, and a dipole inducing layer between them, which increases cell threshold voltage and reduces parasitic capacitance, enabling higher integration density and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine-pattern fabrication to increase integration degree, then integration density improves, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell layout to three-dimensional vertically stacked architecture. Memory cells are arranged in multiple layers stacked along the vertical direction, with word lines, bit lines, and select lines extending in different spatial dimensions. This dimensional change allows significant increase in integration density without requiring proportionally finer pattern dimensions, thereby reducing reliance on increasingly complex fine-pattern fabrication processes.
2Device complexity
If conventional single work function electrode is used in word line, then device structure is simple, but threshold voltage control and power consumption optimization are limited
Solution Approach 1:
The word line electrode is divided into multiple segments along its length, with each segment having a different work function material. Specifically, a first portion of the word line has a first work function and a second portion has a second work function different from the first. This local differentiation allows optimization of threshold voltage control in different regions of the memory cell, improving overall device reliability while maintaining reasonable structural complexity.
3Reliability
If channel doping is used to adjust threshold voltage, then threshold voltage control is achieved, but parasitic capacitance increases and integration density suffers
Solution Approach 1:
Instead of adjusting threshold voltage through channel doping, the patent changes the work function parameter of the electrode materials. By selecting materials with different work functions for different portions of the word line, the threshold voltage is controlled through electrode material selection rather than channel doping. This approach avoids the parasitic capacitance issues associated with doped channels and allows higher integration density.
4Quantity of substance
If three-dimensional vertically stacked memory cells are implemented, then integration density increases, but manufacturing process complexity and alignment precision requirements increase
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete layers including first and second active layers, first and second word lines, first and second bit lines, and first and second select lines. Each layer can be formed and aligned independently through sequential fabrication steps. This segmentation allows for more tolerant alignment processes compared to forming all structures in a single step, as each layer's positioning can be optimized independently, thereby reducing overall alignment precision requirements while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual work function electrode configuration enhances memory cell integration density, reduces power consumption, and maintains refresh characteristics, while the dipole inducing layer adjusts threshold voltage without channel doping, improving overall memory performance.
Implementation Method 1
a dipole inducing layer disposed between the high work function electrode and the gate dielectric layer
Implementation Method 2
a word line laterally oriented in a direction crossing the active layer over the gate dielectric layer and including a low work function electrode and a high work function electrode, the high work function electrode having a higher work function than the low work function electrode
Data Source
AI summary
Present invention relates to a highly-integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, a semiconductor device comprises: an active layer including a channel, the active layer being spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed over the active layer; a word line laterally oriented in a direction crossing the active layer over the gate dielectric layer and including a low work function electrode and a high work function electrode, the high work function electrode having a higher work function than the low work function electrode; and a dipole inducing layer disposed between the high work function electrode and the gate dielectric layer.