3D Semiconductor Memory Layout With Dummy Blocks and Through Vias
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited due to the high cost of miniaturizing fine patterns, and three-dimensional semiconductor memory devices are proposed to address this, but their reliability and efficiency need improvement.
Innovation Solution
A semiconductor memory device with a mold structure featuring stacked gate electrodes, channel structures, and through structures, including memory cell blocks and dummy blocks, to enhance integration density and reliability through a stair-stepped extension region design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional stacked structures by introducing vertical channel structures that extend through multiple gate electrode layers. This dimensional change allows memory cells to be arranged in three dimensions rather than just on a plane, significantly increasing integration density while maintaining manufacturing feasibility through sequential layer formation processes
2Quantity of substance
If three-dimensional stacked structures are implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the three-dimensional structure into discrete stacked layers including alternating gate electrodes and insulating layers, with channel structures segmented into distinct regions. This segmentation allows each layer to be formed and controlled independently, reducing manufacturing complexity while achieving high integration density through vertical stacking
Solution Approach 2:
The patent forms blocking insulating layers and charge storage layers in advance within the channel structures before completing the gate electrode stacking. This preliminary action simplifies subsequent manufacturing steps by pre-establishing critical functional layers that would otherwise require complex post-processing
3Quantity of substance
If fine patterns are miniaturized in two-dimensional devices, then integration density increases, but manufacturing cost increases significantly
Solution Approach 1:
The patent achieves higher integration density by utilizing the vertical dimension through stacked gate electrodes and vertical channel structures, rather than continuing to miniaturize two-dimensional patterns. This approach increases capacity without requiring extremely high-priced equipment for further fine pattern miniaturization
Data Source
AI summary
A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.