3D Memory Asymmetry Reduces Leakage Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining reliability due to disturbances at normal memory cells adjacent to select transistors, which affect the electrical characteristics and data storage efficiency.
Innovation Solution
The semiconductor memory device incorporates a structure with a greater number of drain-side middle dummy memory cells compared to source-side middle dummy memory cells, and a higher number of drain select transistors than source select transistors, to reduce electric field disturbances and enhance electrical characteristics, particularly in the second sub-cell string, where the drain-side middle dummy memory cells are placed at the same height as normal memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of drain-side middle dummy memory cells is increased to reduce electric field disturbances, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by differentiating the number of dummy memory cells between drain-side and source-side. Specifically, the drain-side middle dummy memory cell is configured with a greater number than the source-side middle dummy memory cell, creating asymmetric local structures tailored to the different electrical characteristics and disturbance patterns at each end of the memory cell string. This resolves the contradiction by locally optimizing reliability where needed (drain-side) without uniformly increasing complexity throughout the entire device.
Solution Approach 2:
The patent implements asymmetry by deliberately configuring an unequal number of dummy memory cells at the drain-side versus source-side of the memory cell string. The drain-side middle dummy memory cell has a greater number of cells compared to the source-side, creating an asymmetric structure that addresses the different electrical field disturbance characteristics at each end. This asymmetric configuration improves reliability by better compensating for drain-side disturbances while avoiding unnecessary complexity increases elsewhere in the device.
2Reliability
If drain-side middle dummy memory cells are placed at the same height as normal memory cells, then electrical characteristics are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by positioning drain-side middle dummy memory cells at the same height level as normal memory cells, creating a localized structural arrangement that optimizes electrical characteristics in the drain region. This specific local configuration enhances charge distribution and reduces electric field disturbances at critical locations without requiring uniform height adjustments across the entire memory structure, thereby managing manufacturing precision requirements.
3Reliability
If the number of drain select transistors is increased to reduce leakage current, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by increasing the number of select transistors specifically at the drain-side of the memory cell string, rather than uniformly increasing transistor counts throughout the device. The drain-side select transistor is configured with a greater number than the source-side select transistor, creating localized transistor arrays that better control leakage current at the drain region where it most impacts reliability, while keeping source-side complexity lower.
Solution Approach 2:
The patent implements asymmetry by configuring an unequal number of select transistors at the drain-side versus source-side. The drain-side middle dummy memory cell region has more select transistors compared to the source-side, creating an asymmetric transistor distribution that addresses the different leakage current characteristics and electrical field patterns at each end of the memory cell string. This asymmetric approach improves reliability by better controlling drain-side leakage while avoiding unnecessary complexity increases at the source-side.
Data Source
AI summary
A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the first sub-cell string. The first sub-cell string may have a first group of normal memory cells and at least one source-side middle dummy memory cell coupled to the first sub-cell string and the first group of the normal memory cells. The second sub-cell string may be coupled to a bit line at an end of the second sub-cell string. The second sub-cell string may have a second group of normal memory cells and drain-side middle dummy memory cells coupled to the second group the normal memory cells. The number of the drain-side middle dummy memory cells may be greater than the number of the at least one source-side middle dummy memory cell.