3D Memory Plane Layout With Dummy Structures for Etch Uniformity
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and reducing fabrication complexity while maintaining performance advantages, particularly in vertical memory arrays like 3D NAND Flash memory devices, due to issues such as uneven etch loading and large plane separation regions.
Innovation Solution
The proposed microelectronic device structures reduce or eliminate the plane separation region by using dummy structures and discrete source structures, enhancing packing density and mitigating uneven etch loading, while allowing for grounded or biased read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical memory array architectures are used to increase memory density, then integration density is improved, but uneven etch loading and large plane separation regions occur
Solution Approach 1:
The patent introduces dummy structures (dummy blocks and dummy slots) in specific locations where etch loading needs to be balanced. These dummy structures have the same physical and chemical properties as real memory structures, allowing them to interact with etching processes identically. By strategically placing these dummy structures, the etch loading is equalized across different planes without affecting the functional memory regions.
Solution Approach 2:
The dummy structures act as intermediary elements that mediate between the etching process and the vertical memory structures. They serve as placeholders that absorb excess etching activity or provide additional etching targets in regions where etch loading is insufficient, thereby balancing the overall etch loading distribution across the device.
2Area of stationary object
If plane separation regions are reduced to increase packing density, then integration density is improved, but fabrication difficulty increases
Solution Approach 1:
The patent segments the device into functional regions and dummy regions, where dummy structures are placed in non-functional areas. This segmentation allows the reduction of plane separation regions in functional areas to improve packing density, while dummy structures in non-functional areas maintain etch loading balance and simplify fabrication by providing etching references and process control points.
3Quantity of substance
If feature dimensions are reduced to increase integration density, then memory density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the physical and chemical parameters of dummy structures to match those of real memory structures. By ensuring that dummy structures have identical material composition, dimensions, and geometric characteristics, they respond to etching and other manufacturing processes in the same way as functional structures, providing process control references that help maintain manufacturing precision even as feature dimensions are reduced.
Data Source
AI summary
A microelectronic device may include a plane comprising blocks horizontally extending in parallel in a first direction and horizontally alternating with slot structures in a second direction orthogonal to the first direction. The blocks may include tiers individually including conductive material and insulative material vertically neighboring the conductive material. The device may also include an additional plane horizontally neighboring the plane in the second direction and including additional blocks similar to the blocks. At least one source structure may vertically underlie and horizontally overlap horizontal areas of the plane and the additional plane. A plane separation region may be interposed between the plane and the additional plane in the second direction. The plane separation region may have a horizontal width in the second direction that is less than or equal to a combined horizontal width in the second direction of one of the blocks and two of the slot structures.