3D Semiconductor Memory Device Dummy Interconnection Structure
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Solution Overview
Problem
Three-dimensional (3D) semiconductor memory devices face limitations in integration density and electrical characteristics due to the need for high-priced equipment to form finer patterns, which restricts the increase in integration density and leads to increased resistance and noise in transmitting common source voltage.
Innovation Solution
A 3D semiconductor memory device design featuring a peripheral circuit structure on a first substrate with a dummy interconnection structure under a second substrate, including stacked interconnection lines and vias, and vertical channel structures with conductive spacers and bit lines, which reduces resistance and improves electrical characteristics by uniformly distributing metal and applying common source voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher-priced apparatuses are used to form finer patterns, then integration density increases, but manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. This dimensional change allows integration density to increase without requiring finer patterning, thereby avoiding the need for expensive manufacturing apparatus while achieving higher capacity
2Quantity of substance
If integration density increases in 2D devices, then more memory cells are packed, but resistance and noise increase
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent reduces the number of interconnection layers required compared to planar expansion. This shortens current paths and reduces resistance and noise, maintaining electrical characteristics while achieving higher integration density
Solution Approach 2:
The patent divides the memory structure into multiple stacked cell layers with shared source and bit lines. This segmentation allows independent optimization of each layer while sharing common interconnections, reducing overall resistance and noise in the system
Data Source
AI summary
A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.