3D Memory Bonding Structure With Dummy Layers Against Warpage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity, particularly in achieving high-capacity storage through three-dimensional memory cell arrangements without compromising reliability and efficiency.
Innovation Solution
The semiconductor device incorporates a dual-substrate structure with metal bonding layers and insulating dummy pattern layers, where the second metal bonding layers have a specific thickness and the dummy pattern layers are made of insulating material, providing improved bonding and reducing warpage, thus enhancing data storage capacity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but manufacturing complexity and reliability issues arise
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure by vertically stacking multiple substrate structures (first substrate structure with circuit elements, second substrate structure with memory cells) connected through metal bonding layers. This vertical stacking enables increased storage capacity by utilizing the third dimension (height) rather than only horizontal expansion.
Solution Approach 2:
The memory device is divided into multiple independent substrate structures (first substrate structure containing circuit elements, second substrate structure containing memory cells) that can be manufactured separately and then bonded together. This segmentation allows for specialized optimization of each substrate and simplifies the manufacturing process by enabling parallel production of multiple substrates before final assembly.
2Quantity of substance
If three-dimensionally arranged memory cells are used, then data storage capacity is increased, but warpage issues compromise reliability
Solution Approach 1:
The patent introduces dummy pattern layers (insulating material) between the metal bonding layers to create a more uniform thickness distribution across the bonding interface. This homogenization of the bonding structure compensates for the non-uniform stress distribution caused by the three-dimensional memory cell arrangement, thereby reducing warpage and improving bonding reliability.
Solution Approach 2:
The dummy pattern layers are pre-positioned between the metal bonding layers to counteract the warpage forces that will arise during or after the bonding process. By introducing these compensatory insulating structures in advance, the patent prevents warpage-induced bonding failures before they occur.
3Reliability
If metal bonding layers are used to connect substrate structures, then electrical connection is achieved, but warpage occurs affecting bonding quality
Solution Approach 1:
The patent introduces insulating dummy pattern layers as intermediary structures between the metal bonding layers. These dummy patterns act as mediators that distribute mechanical stress uniformly across the bonding interface, preventing warpage while maintaining the electrical connection function of the metal bonding layers. The dummy patterns are strategically positioned to fill gaps and create a more uniform bonding surface.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes a first substrate structure (S1) including a substrate (201), circuit elements (220) on the substrate (201), a first interconnection structure (270, 280) on the circuit elements (220), and first metal bonding layers (298) on the first interconnection structure (270, 280); and a second substrate structure (S2) connected to the first substrate structure (S 1), and the second substrate structure (S2) includes: a plating layer (101); gate electrodes (130) stacked and spaced apart from each other in a first direction below the plating layer (101); channel structures (CH) penetrating through the gate electrodes (130) and extending in the first direction; a separation region (MS) penetrating through the gate electrodes (130) and extending in a second direction (X); a second interconnection structure (150, 155, 170, 180) below the gate electrodes (130) and the channel structures (CH); second metal bonding layers (198) below the second interconnection structure (150, 155, 170, 180) and connected to the first metal bonding layers (298); and dummy pattern layers (160) between the second metal bonding layers (198), extending in the second direction (X), and including an insulating material.