3D Memory Through-Plug Layout With Dummy Plugs for Alignment Reliability
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the high cost and complexity of processing equipment required for fine pattern formation, necessitating the development of three-dimensional semiconductor memory devices with improved reliability and integration.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a peripheral circuit structure with vertically stacked electrodes, a planarized dielectric layer, and strategically placed dummy through plugs to enhance integration and reduce manufacturing costs, while maintaining reliability through a stepwise electrode structure and vertical channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use fine pattern formation to increase integration, then integration density improves, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked above the substrate, with word lines, bit lines, and channel structures arranged in vertical configurations. This dimensional change allows significantly higher integration density without requiring proportionally finer lithographic patterns, thereby reducing manufacturing complexity while increasing capacity.
2Area of stationary object
If peripheral through plugs are placed close to electrode structures to reduce area, then device area decreases, but manufacturing precision and reliability may deteriorate
Solution Approach 1:
The patent introduces dummy through plugs with different properties than functional through plugs. These dummy plugs have modified dimensions, materials, or electrical characteristics to provide localized compensation effects. By adjusting the properties of specific through plugs based on their location relative to electrode structures, the patent optimizes both area utilization and manufacturing precision in different regions of the device.
Solution Approach 2:
The patent places dummy through plugs strategically near electrode structures to compensate for potential manufacturing variations before they affect device performance. These dummy structures serve as buffer elements that absorb or mitigate the impact of alignment errors, etch depth variations, or material property deviations, thereby maintaining reliability even when functional through plugs are positioned close to sensitive electrode structures.
3Reliability
If dummy through plugs are added around peripheral through plugs to improve reliability, then manufacturing reliability improves, but device complexity increases
Solution Approach 1:
The patent creates simplified copies of functional through plugs by forming dummy through plugs using the same fabrication processes and materials. These dummy structures replicate key characteristics of functional through plugs without requiring separate fabrication steps or additional material deposition. By copying the essential features of through plugs, the patent improves reliability through redundancy while minimizing increases in device complexity and manufacturing overhead.
Data Source
AI summary
A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.