3D Memory Electrode Structure With Dummy Vertical Separation
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and integration density while maintaining reliability and ease of fabrication.
Innovation Solution
The semiconductor device incorporates a structure with electrodes and insulating layers stacked vertically, featuring middle separation structures, vertical structures, and dummy vertical structures with specific patterns to enhance integration density and reliability, including dummy gapfill insulating and semiconductor patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to increase data storage capacity, then integration density is improved, but device complexity increases
Solution Approach 1:
The device is divided into multiple stacks, each containing memory cells arranged in a three-dimensional configuration. Each stack is further segmented into memory cell regions and dummy structure regions, allowing complex 3D memory cells to be organized into manageable modular units that can be fabricated using standardized processes
Solution Approach 2:
Dummy structures are introduced as intermediary elements between active memory cell regions. These dummy structures include dummy gapfill insulating patterns, dummy vertical semiconductor patterns, and dummy data storage patterns that replicate the geometry of functional components without storing data, serving as placeholders to maintain structural consistency and simplify fabrication
2Reliability
If middle separation structures are added to horizontally separate electrode portions, then reliability is improved, but device complexity increases
Solution Approach 1:
Middle separation structures are extracted as distinct components from the continuous electrode structure. These separation structures physically divide and isolate horizontally adjacent electrode portions, preventing electrical interference and improving device reliability by eliminating potential failure modes related to electrode coupling
Solution Approach 2:
The middle separation structures are strategically positioned only in regions where horizontal electrode separation is needed, rather than uniformly throughout the entire device. This localized approach provides reliability improvements at critical interfaces while minimizing the overall addition of structural complexity
3Manufacturing precision
If dummy vertical structures with multiple patterns are added, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Dummy vertical structures are prepared in advance with pre-defined geometric configurations that match the dimensions and shapes of functional vertical structures. The dummy gapfill insulating patterns, dummy vertical semiconductor patterns, and dummy data storage patterns are formed using the same fabrication processes as their functional counterparts, establishing precise dimensional references before final device assembly
Solution Approach 2:
The dummy vertical structures are designed to be homogeneous in geometry and material composition with the functional vertical structures they replace or accompany. This homogeneity ensures that etching, deposition, and other fabrication processes interact with dummy and functional structures identically, maintaining consistent manufacturing precision across the entire wafer
Data Source
AI summary
A semiconductor device may include a semiconductor substrate, an electrode structure including electrodes and insulating layers, which are alternately stacked on the semiconductor substrate in a vertical direction, middle separation structures that penetrate an upper portion of the electrode structure, and horizontally separate portions of the electrodes located in the upper portion from each other, vertical structures penetrating through the electrode structure, and dummy vertical structures penetrating through the electrode structure and vertically overlapped with the middle separation structures. Each of the dummy vertical structures may include a dummy gapfill insulating pattern, a dummy vertical semiconductor pattern enclosing a side surface of the dummy gapfill insulating pattern, and a dummy data storage pattern enclosing a side surface of the dummy vertical semiconductor pattern. The uppermost portion of the dummy vertical semiconductor pattern may be in contact with a side surface of the dummy data storage pattern.