3D Memory Cell Layout With Dummy Vertical Structures for Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and improving reliability and integration of memory cells.
Innovation Solution
The semiconductor device incorporates a substrate with a cell array region and connection region, featuring ground selection gate patterns, cell gate patterns vertically stacked on these, separation structures, and dummy vertical structures that extend vertically into the cell gate patterns, enhancing the integration and reliability of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by vertically stacking multiple memory cell layers on the substrate. This dimensional change enables increased data storage capacity by utilizing the vertical space above the substrate surface, allowing memory cells to be organized in multiple stacked layers rather than a single plane.
Solution Approach 2:
The patent implements nested structures by placing memory cell layers, separation structures, and dummy vertical structures within and around each other in the vertical dimension. The separation structures extend into the cell gate patterns, and dummy vertical structures are positioned between separation structures, creating a nested arrangement that optimizes space utilization while maintaining organizational clarity.
2Reliability
If separation structures and dummy vertical structures are added to the memory cell configuration, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory cell array into distinct regions by introducing separation structures that extend vertically into the cell gate patterns. These separation structures create segmented zones between adjacent memory cell strings, improving reliability by isolating potential failure regions and preventing defect propagation across the entire array.
Solution Approach 2:
The patent introduces dummy vertical structures as intermediary elements positioned between the separation structures and the memory cell components. These dummy structures serve as buffer or mediator elements that can absorb stress, prevent direct contact between potentially conflicting structures, and enhance the overall structural integrity and reliability of the three-dimensional configuration.
Data Source
AI summary
A semiconductor device includes a substrate including a cell array region and a connection region, a plurality of ground selection gate patterns spaced apart from each other, a plurality of cell gate patterns vertically stacked on the plurality of ground selection gate patterns, separation structures vertically extending into the cell gate patterns and disposed between the plurality of ground selection gate patterns and spaced apart from each other in a first direction in the connection region, and dummy vertical structures disposed between the separation structures that are adjacent in the first direction and between a first ground selection gate pattern and a second ground selection gate pattern adjacent to the first ground selection gate pattern. Each of the dummy vertical structures includes a vertical portion that vertically extends into the cell gate patterns and an extension that protrudes horizontally from the vertical portion.