3D Non-Volatile Memory Dummy Transistor Programming

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Solution Overview

Problem

Non-volatile memory devices face operational inefficiencies due to non-uniform etching processes and impurity diffusion, leading to variations in pad heights and junction overlap, which affect the performance of memory strings.

Innovation Solution

Incorporating dummy transistors in memory strings that are programmed to different degrees based on the height of the pads and junction overlap, ensuring uniform threshold voltage and improved operational characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the etching process is performed during manufacturing, then the memory strings are formed, but the pad heights become non-uniform due to process variations

Engineering Contradiction:
Improvememory string formation efficiencyVSAvoidpad height uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by adjusting the programming degree of dummy transistors based on pad height measurements. Memory strings with higher pads are programmed to a greater degree, while those with lower pads are programmed to a lesser degree, thereby compensating for the non-uniformity introduced by the etching process and achieving uniform threshold voltages across all memory strings.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If impurity diffusion occurs from pad to channel layer, then junction overlap is formed, but operational efficiency decreases due to variations in junction overlap

Engineering Contradiction:
Improvejunction formationVSAvoidoperational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent compensates for variations in junction overlap caused by impurity diffusion by adjusting the programming parameters of dummy transistors. By measuring pad heights and calculating appropriate programming degrees, the system optimizes the electrical characteristics of memory strings with different junction overlap values, thereby maintaining high operational efficiency despite the presence of impurity diffusion variations.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If dummy transistors are added to memory strings, then threshold voltage uniformity is improved, but device complexity increases

Engineering Contradiction:
Improvethreshold voltage uniformityVSAvoidmemory string structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by adding dummy transistors only to specific memory strings that require threshold voltage adjustment, rather than uniformly to all memory strings. The number and programming degree of dummy transistors are tailored to the specific needs of each memory string based on its pad height and junction overlap characteristics, thereby achieving threshold voltage uniformity while minimizing the increase in device complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and operational efficiency of semiconductor devices by compensating for physical structure differences, resulting in uniform electrical characteristics across memory strings.

Implementation Method 1

the diffusion of impurities from the pad to the channel layer results in differences in junction overlap

Methodology Applied
Scientific EffectImpurity diffusion: Diffusion

Data Source

PatentUS11074977B2Three-dimensional non-volatile memory device and method of manufacturing the same
Publication Date: 2021.07.27 SK HYNIX INC
  • US11074977B2 patent drawing
  • US11074977B2 patent drawing
  • US11074977B2 patent drawing

AI summary

A semiconductor device includes a memory block including a plurality of memory strings, each of the plurality of memory strings including one or more dummy transistors, wherein each of the dummy transistors, included in the plurality of memory strings, is programmed to different degrees according to a junction overlap of each of the memory strings.